X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/4d90f272baf43caf90927ca7e893518d526649e5..0dea04d38b6864e9734f5a0e556cc088887835bd:/LCDC.v

diff --git a/LCDC.v b/LCDC.v
index a8bec01..0e1b569 100644
--- a/LCDC.v
+++ b/LCDC.v
@@ -63,8 +63,8 @@ module LCDC(
 	reg [8:0] posx = 9'h000;
 	reg [7:0] posy = 8'h00;
 	
-	wire vraminuse = (posx < 163);
-	wire oaminuse = (posx > 369);
+	wire vraminuse = (posx < 163) && (posy < 144);
+	wire oaminuse = (posx > 369) && (posy < 144);
 	
 	wire display = (posx > 2) && (posx < 163) && (posy < 144);
 	
@@ -81,7 +81,7 @@ module LCDC(
 	assign lcdhs = (posx == 455);
 	assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
 	assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
-	assign lcdb = display ? {(vypos < 8) ? 2'b11 : 2'b00} : 2'b00;
+	assign lcdb = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;
 	
 	reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
 	assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
@@ -137,7 +137,7 @@ module LCDC(
 	// The new tile data is latched and ready when vxpos[2:0] is 3'b000!
 	wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]};
 	reg [7:0] tileno;
-	wire [10:0] tileaddr = {tileno, vypos[2:1]};
+	wire [10:0] tileaddr = {tileno, vypos[2:0]};
 	reg [7:0] tilehigh, tilelow;
 	assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]};
 	
@@ -148,39 +148,39 @@ module LCDC(
 	wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
 	
 	always @(negedge clk)
-		if ((vraminuse && ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))) || decode_bgmap1) begin
+		if ((vraminuse && ((posx == 1) || (vxpos[2:0] == 3'b110))) || decode_bgmap1) begin
 			tileno <= bgmap1[bgmapaddr_in];
-			if (wr && decode_bgmap1)
+			if (wr && decode_bgmap1 && ~vraminuse)
 				bgmap1[bgmapaddr_in] <= data;
 		end
 	
 	always @(negedge clk)
-		if ((vraminuse && ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111)))) || decode_tiledata) begin
+		if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_tiledata) begin
 			tilehigh <= tiledatahigh[tileaddr_in];
 			tilelow <= tiledatalow[tileaddr_in];
-			if (wr && addr[0] && decode_tiledata)
+			if (wr && addr[0] && decode_tiledata && ~vraminuse)
 				tiledatahigh[tileaddr_in] <= data;
-			if (wr && ~addr[0] && decode_tiledata)
+			if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
 				tiledatalow[tileaddr_in] <= data;
 		end
   
 	/***** Bus interface *****/
 	assign data = rd ?
-			(addr == `ADDR_LCDC) ? rLCDC :
-			(addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
-			(addr == `ADDR_SCY) ? rSCY :
-			(addr == `ADDR_SCX) ? rSCX :
-			(addr == `ADDR_LY) ? posy :
-			(addr == `ADDR_LYC) ? rLYC :
-			(addr == `ADDR_BGP) ? rBGP :
-			(addr == `ADDR_OBP0) ? rOBP0 :
-			(addr == `ADDR_OBP1) ? rOBP1 :
-			(addr == `ADDR_WY) ? rWY :
-			(addr == `ADDR_WX) ? rWX :
-			(decode_tiledata && addr[0]) ? tilehigh :
-			(decode_tiledata && ~addr[0]) ? tilelow :
-			(decode_bgmap1) ? tileno :
-			8'bzzzzzzzz :
+			((addr == `ADDR_LCDC) ? rLCDC :
+			 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
+			 (addr == `ADDR_SCY) ? rSCY :
+			 (addr == `ADDR_SCX) ? rSCX :
+			 (addr == `ADDR_LY) ? posy :
+			 (addr == `ADDR_LYC) ? rLYC :
+			 (addr == `ADDR_BGP) ? rBGP :
+			 (addr == `ADDR_OBP0) ? rOBP0 :
+			 (addr == `ADDR_OBP1) ? rOBP1 :
+			 (addr == `ADDR_WY) ? rWY :
+			 (addr == `ADDR_WX) ? rWX :
+			 (decode_tiledata && addr[0]) ? tilehigh :
+			 (decode_tiledata && ~addr[0]) ? tilelow :
+			 (decode_bgmap1) ? tileno :
+			 8'bzzzzzzzz) :
 		8'bzzzzzzzz;
   
 	always @(negedge clk)