X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/3ad960bdb71efcbb1dfd436163085da0d70eb699..5509558d05f30339f3393f02f67e8854cbe25a00:/insn_alu8.v

diff --git a/insn_alu8.v b/insn_alu8.v
index 8470e27..6abcb90 100644
--- a/insn_alu8.v
+++ b/insn_alu8.v
@@ -1,20 +1,18 @@
 `ifdef EXECUTE
 	`INSN_ALU8: begin
-		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-			// fffffffff fuck your shit, read from (HL) :(
-			rd <= 1;
-			address <= {registers[`REG_H], registers[`REG_L]};
-		end else begin
+		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
+			`EXEC_READ(_HL);
+		else begin
 			`EXEC_NEWCYCLE;
 			`EXEC_INC_PC;
 			case (opcode[2:0])
-			`INSN_reg_A:	tmp <= registers[`REG_A];
-			`INSN_reg_B:	tmp <= registers[`REG_B];
-			`INSN_reg_C:	tmp <= registers[`REG_C];
-			`INSN_reg_D:	tmp <= registers[`REG_D];
-			`INSN_reg_E:	tmp <= registers[`REG_E];
-			`INSN_reg_H:	tmp <= registers[`REG_H];
-			`INSN_reg_L:	tmp <= registers[`REG_L];
+			`INSN_reg_A:	tmp <= `_A;
+			`INSN_reg_B:	tmp <= `_B;
+			`INSN_reg_C:	tmp <= `_C;
+			`INSN_reg_D:	tmp <= `_D;
+			`INSN_reg_E:	tmp <= `_E;
+			`INSN_reg_H:	tmp <= `_H;
+			`INSN_reg_L:	tmp <= `_L;
 			`INSN_reg_dHL:	tmp <= rdata;
 			endcase
 		end
@@ -28,83 +26,68 @@
 		end else begin		/* Actually do the computation! */
 			case (opcode[5:3])
 			`INSN_alu_ADD: begin
-				registers[`REG_A] <=
-					registers[`REG_A] + tmp;
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A + tmp;
+				`_F <=	{ /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
 					  /* N */ 1'b0,
-					  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-					  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-					  registers[`REG_F][3:0]
+					  /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_ADC: begin
-				registers[`REG_A] <=
-					registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A + tmp + {7'b0,`_F[4]};
+				`_F <=	{ /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
 					  /* N */ 1'b0,
-					  /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
-					  /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
-					  registers[`REG_F][3:0]
+					  /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_SUB: begin
-				registers[`REG_A] <=
-					registers[`REG_A] - tmp;
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A - tmp;
+				`_F <=	{ /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
 					  /* N */ 1'b1,
-					  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-					  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-					  registers[`REG_F][3:0]
+					  /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+					  /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_SBC: begin
-				registers[`REG_A] <=
-					registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A - (tmp + {7'b0,`_F[4]});
+				`_F <= 	{ /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
 					  /* N */ 1'b1,
-					  /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
-					  /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
-					  registers[`REG_F][3:0]
+					  /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
+					  /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_AND: begin
-				registers[`REG_A] <=
-					registers[`REG_A] & tmp;
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A & tmp;
+				`_F <=	{ /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
 					  3'b010,
-					  registers[`REG_F][3:0]
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_OR: begin
-				registers[`REG_A] <=
-					registers[`REG_A] | tmp;
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A | tmp;
+				`_F <=	{ /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
 					  3'b000,
-					  registers[`REG_F][3:0]
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_XOR: begin
-				registers[`REG_A] <=
-					registers[`REG_A] ^ tmp;
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+				`_A <= `_A ^ tmp;
+				`_F <=	{ /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
 					  3'b000,
-					  registers[`REG_F][3:0]
+					  `_F[3:0]
 					};
 			end
 			`INSN_alu_CP: begin
-				registers[`REG_F] <=
-					{ /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+				`_F <=	{ /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
 					  /* N */ 1'b1,
-					  /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-					  /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-					  registers[`REG_F][3:0]
+					  /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+					  /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+					  `_F[3:0]
 					};
 			end
 			default: