X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/2f55f80959676970f85a02a9a968668ae2113dda..634ce02ca41547deda6e98f0e16a81f849bb130c:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 9bc60a8..fa9ed0b 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -22,15 +22,24 @@
 `define STATE_WRITEBACK		2'h3
 
 `define INSN_LD_reg_imm8	8'b00xxx110
-`define INSN_imm8_reg_A		3'b111
-`define INSN_imm8_reg_B		3'b000
-`define INSN_imm8_reg_C		3'b001
-`define INSN_imm8_reg_D		3'b010
-`define INSN_imm8_reg_E		3'b011
-`define INSN_imm8_reg_H		3'b100
-`define INSN_imm8_reg_L		3'b101
-`define INSN_imm8_reg_dHL	3'b110
-
+`define INSN_HALT				8'b01110110
+`define INSN_LD_HL_reg		8'b01110xxx
+`define INSN_LD_reg_HL		8'b01xxx110
+`define INSN_LD_reg_reg		8'b01xxxxxx
+`define INSN_LD_reg_imm16	8'b00xx0001
+`define INSN_LD_SP_HL		8'b11111001
+`define INSN_reg_A		3'b111
+`define INSN_reg_B		3'b000
+`define INSN_reg_C		3'b001
+`define INSN_reg_D		3'b010
+`define INSN_reg_E		3'b011
+`define INSN_reg_H		3'b100
+`define INSN_reg_L		3'b101
+`define INSN_reg_dHL	3'b110
+`define INSN_reg16_BC	2'b00
+`define INSN_reg16_DE	2'b01
+`define INSN_reg16_HL	2'b10
+`define INSN_reg16_SP	2'b11
 module GBZ80Core(
 	input clk,
 	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
@@ -49,6 +58,8 @@ module GBZ80Core(
 	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
 	reg rd = 1, wr = 0, newcycle = 1;
 	
+	reg [7:0] tmp;					/* Generic temporary reg. */
+	
 	reg [7:0] buswdata;
 	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
 	
@@ -84,6 +95,7 @@ module GBZ80Core(
 			if (newcycle) begin
 				opcode <= busdata;
 				rdata <= busdata;
+				newcycle <= 0;
 				cycle <= 0;
 			end else
 				if (rd) rdata <= busdata;
@@ -104,12 +116,11 @@ module GBZ80Core(
 				0:	begin
 						`EXEC_INC_PC;
 						`EXEC_NEXTADDR_PCINC;
-						newcycle <= 0;
 						rd <= 1;
 					end
 				1: begin
 						`EXEC_INC_PC;
-						if (opcode[5:3] == `INSN_imm8_reg_dHL) begin
+						if (opcode[5:3] == `INSN_reg_dHL) begin
 							address <= {registers[`REG_H], registers[`REG_L]};
 							wdata <= rdata;
 							rd <= 0;
@@ -123,26 +134,180 @@ module GBZ80Core(
 					end
 				endcase
 			end
+			`INSN_HALT: begin
+				`EXEC_NEWCYCLE;
+				/* XXX Interrupts needed for HALT. */
+			end
+			`INSN_LD_HL_reg: begin
+				case (cycle)
+				0:	begin
+						case (opcode[2:0])
+						`INSN_reg_A:	begin wdata <= registers[`REG_A]; end
+						`INSN_reg_B:	begin wdata <= registers[`REG_B]; end
+						`INSN_reg_C:	begin wdata <= registers[`REG_C]; end
+						`INSN_reg_D:	begin wdata <= registers[`REG_D]; end
+						`INSN_reg_E:	begin wdata <= registers[`REG_E]; end
+						`INSN_reg_H:	begin wdata <= registers[`REG_H]; end
+						`INSN_reg_L:	begin wdata <= registers[`REG_L]; end
+						endcase
+						address <= {registers[`REG_H], registers[`REG_L]};
+						wr <= 1; rd <= 0;
+					end
+				1:	begin
+						`EXEC_INC_PC;
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
+			`INSN_LD_reg_HL: begin
+				case(cycle)
+				0: begin
+						address <= {registers[`REG_H], registers[`REG_L]};
+						wr <= 0; rd <= 1;
+					end
+				1: begin
+						tmp <= rdata;
+						`EXEC_INC_PC;
+						`EXEC_NEWCYCLE;
+					end
+				endcase
+			end
+			`INSN_LD_reg_reg: begin
+				`EXEC_INC_PC;
+				`EXEC_NEWCYCLE;
+				case (opcode[2:0])
+				`INSN_reg_A:	begin tmp <= registers[`REG_A]; end
+				`INSN_reg_B:	begin tmp <= registers[`REG_B]; end
+				`INSN_reg_C:	begin tmp <= registers[`REG_C]; end
+				`INSN_reg_D:	begin tmp <= registers[`REG_D]; end
+				`INSN_reg_E:	begin tmp <= registers[`REG_E]; end
+				`INSN_reg_H:	begin tmp <= registers[`REG_H]; end
+				`INSN_reg_L:	begin tmp <= registers[`REG_L]; end
+				endcase
+			end
+			`INSN_LD_reg_imm16: begin
+				`EXEC_INC_PC;
+				case (cycle)
+				0:	begin
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				1:	begin
+						`EXEC_NEXTADDR_PCINC;
+						rd <= 1;
+					end
+				2: begin `EXEC_NEWCYCLE; end
+				endcase
+			end
+			`INSN_LD_SP_HL: begin
+				case (cycle)
+				0:	begin
+						rd <= 0;
+						address <= 16'bxxxxxxxxxxxxxxxx;
+						tmp <= registers[`REG_H];
+					end
+				1:	begin
+						`EXEC_NEWCYCLE;
+						`EXEC_INC_PC;
+						tmp <= registers[`REG_L];
+					end
+				endcase
+			end
+			default:
+				$stop;
 			endcase
 			state <= `STATE_WRITEBACK;
 		end
 		`STATE_WRITEBACK: begin
 			casex (opcode)
-				`INSN_LD_reg_imm8:
-					case (cycle)
-					0: cycle <= 1;
-					1: case (opcode[5:3])
-						`INSN_imm8_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
-						`INSN_imm8_reg_dHL:	cycle <= 2;
-						endcase
-					2: cycle <= 0;
+			`INSN_LD_reg_imm8:
+				case (cycle)
+				0: cycle <= 1;
+				1: case (opcode[5:3])
+					`INSN_reg_A:	begin registers[`REG_A] <= rdata; cycle <= 0; end
+					`INSN_reg_B:	begin registers[`REG_B] <= rdata; cycle <= 0; end
+					`INSN_reg_C:	begin registers[`REG_C] <= rdata; cycle <= 0; end
+					`INSN_reg_D:	begin registers[`REG_D] <= rdata; cycle <= 0; end
+					`INSN_reg_E:	begin registers[`REG_E] <= rdata; cycle <= 0; end
+					`INSN_reg_H:	begin registers[`REG_H] <= rdata; cycle <= 0; end
+					`INSN_reg_L:	begin registers[`REG_L] <= rdata; cycle <= 0; end
+					`INSN_reg_dHL:	cycle <= 2;
 					endcase
+				2: cycle <= 0;
+				endcase
+			`INSN_HALT: begin
+				/* Nothing needs happen here. */
+				/* XXX Interrupts needed for HALT. */
+			end
+			`INSN_LD_HL_reg: begin
+				case (cycle)
+				0: cycle <= 1;
+				1: cycle <= 0;
+				endcase
+			end
+			`INSN_LD_reg_HL: begin
+				case (cycle)
+				0:	cycle <= 1;
+				1:	begin
+						case (opcode[5:3])
+						`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
+						`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
+						`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
+						`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
+						`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
+						`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
+						`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+						endcase
+						cycle <= 0;
+					end
+				endcase
+			end
+			`INSN_LD_reg_reg: begin
+				case (opcode[5:3])
+				`INSN_reg_A:	begin registers[`REG_A] <= tmp; end
+				`INSN_reg_B:	begin registers[`REG_B] <= tmp; end
+				`INSN_reg_C:	begin registers[`REG_C] <= tmp; end
+				`INSN_reg_D:	begin registers[`REG_D] <= tmp; end
+				`INSN_reg_E:	begin registers[`REG_E] <= tmp; end
+				`INSN_reg_H:	begin registers[`REG_H] <= tmp; end
+				`INSN_reg_L:	begin registers[`REG_L] <= tmp; end
+				endcase
+			end
+			`INSN_LD_reg_imm16: begin
+				case (cycle)
+				0:	cycle <= 1;
+				1:	begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	registers[`REG_C] <= rdata;
+						`INSN_reg16_DE:	registers[`REG_E] <= rdata;
+						`INSN_reg16_HL:	registers[`REG_L] <= rdata;
+						`INSN_reg16_SP:	registers[`REG_SPL] <= rdata;
+						endcase
+						cycle <= 2;
+					end
+				2: begin
+						case (opcode[5:4])
+						`INSN_reg16_BC:	registers[`REG_B] <= rdata;
+						`INSN_reg16_DE:	registers[`REG_D] <= rdata;
+						`INSN_reg16_HL:	registers[`REG_H] <= rdata;
+						`INSN_reg16_SP:	registers[`REG_SPH] <= rdata;
+						endcase
+						cycle <= 0;
+					end
+				endcase
+			end
+			`INSN_LD_SP_HL: begin
+				case (cycle)
+				0: begin
+						cycle <= 1;
+						registers[`REG_SPH] <= tmp;
+					end
+				1: begin
+						cycle <= 0;
+						registers[`REG_SPL] <= tmp;
+					end
+				endcase
+			end
 			endcase
 			state <= `STATE_FETCH;
 		end