X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/2e642f1f5c3cb12c3a34983d9fbdd0141ca34931..7d9d69c71187b4891b2281ab58ab8360e43290c2:/GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index fc77377..3bc2b16 100644
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -702,30 +702,31 @@ module InternalRAM(
 	end
 endmodule
 
-//module Switches(
-//	input [15:0] address,
-//	inout [7:0] data,
-//	input clk,
-//	input wr, rd,
-//	input [7:0] switches,
-//	output reg [7:0] ledout);
+module Switches(
+	input [15:0] address,
+	inout [7:0] data,
+	input clk,
+	input wr, rd,
+	input [7:0] switches,
+	output reg [7:0] ledout);
 	
-//	wire decode = address == 16'hFF51;
-//	reg [7:0] odata;
-//	wire idata = data;
-//	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	wire decode = address == 16'hFF51;
+	reg [7:0] odata;
+	wire idata = data;
+	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-//	always @(negedge clk)
-//	begin
-//		if (decode && rd)
-//			odata <= switches;
-//		else if (decode && wr)
-//			ledout <= data;
-//	end
-//endmodule
+	always @(negedge clk)
+	begin
+		if (decode && rd)
+			odata <= switches;
+		else if (decode && wr)
+			ledout <= data;
+	end
+endmodule
 
 module CoreTop(
-	input iclk, xtal,
+	input xtal,
+	input [1:0] switches,
 	output wire [7:0] leds,
 	output serio,
 	output wire [3:0] digits,
@@ -740,7 +741,9 @@ module CoreTop(
 	wire [7:0] data;
 	wire wr, rd;
 	
-	assign leds = iclk?{rd,wr,addr[5:0]}:data[7:0];
+	wire [7:0] ledout;
+	assign leds = switches[1] ? (switches[0]?{rd,wr,addr[5:0]}:data[7:0])
+						: ledout;
 
 	GBZ80Core core(
 		.clk(clk),
@@ -758,12 +761,29 @@ module CoreTop(
 	
 	AddrMon amon(
     .addr(addr), 
-    .clk(xtal), 
+    .clk(clk), 
     .digit(digits), 
     .out(seven)
     );
-	
-	assign serio = 0;
+	 
+	Switches sw(
+		.address(addr),
+		.data(data),
+		.clk(clk),
+		.wr(wr),
+		.rd(rd),
+		.ledout(ledout),
+		.switches(0)
+		);
+
+	UART nouart (
+    .clk(clk), 
+    .wr(wr), 
+    .rd(rd), 
+    .addr(addr), 
+    .data(data), 
+    .serial(serio)
+    );
 endmodule
 
 module TestBench();