X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/2e642f1f5c3cb12c3a34983d9fbdd0141ca34931..4da100650a5d23c0cb3407c6fadbbebae68e5ed6:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index fc77377..1bc8f78 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -37,6 +37,13 @@ `define INSN_RST 8'b11xxx111 `define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET `define INSN_CALL 8'b11001101 +`define INSN_JP_imm 8'b11000011 +`define INSN_JPCC_imm 8'b110xx010 + +`define INSN_cc_NZ 2'b00 +`define INSN_cc_Z 2'b01 +`define INSN_cc_NC 2'b10 +`define INSN_cc_C 2'b11 `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 @@ -423,6 +430,34 @@ module GBZ80Core( end endcase end + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 1: begin + `EXEC_INC_PC; + `EXEC_NEXTADDR_PCINC; + rd <= 1; + end + 2: begin + if (!opcode[0]) begin // i.e., JP cc,nn + /* We need to check the condition code to bail out. */ + case (opcode[4:3]) + `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_Z: if (!registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end + `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + `INSN_cc_C: if (!registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end + endcase + end + end + 3: begin + `EXEC_NEWCYCLE; + end + endcase + end default: $stop; endcase @@ -656,6 +691,15 @@ module GBZ80Core( end endcase end + `INSN_JP_imm,`INSN_JPCC_imm: begin + case (cycle) + 0: begin /* type F */ end + 1: tmp <= rdata; // tmp contains newpcl + 2: tmp2 <= rdata; // tmp2 contains newpch + 3: {registers[`REG_PCH],registers[`REG_PCL]} <= + {tmp2,tmp}; + endcase + end default: $stop; endcase @@ -663,155 +707,3 @@ module GBZ80Core( end endcase endmodule - -`timescale 1ns / 1ps -module ROM( - input [15:0] address, - inout [7:0] data, - input clk, - input wr, rd); - - reg [7:0] rom [2047:0]; - initial $readmemh("rom.hex", rom); - - wire decode = address[15:13] == 0; - wire [7:0] odata = rom[address[11:0]]; - assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - //assign data = rd ? odata : 8'bzzzzzzzz; -endmodule - -module InternalRAM( - input [15:0] address, - inout [7:0] data, - input clk, - input wr, rd); - - reg [7:0] ram [8191:0]; - - wire decode = (address >= 16'hC000) && (address < 16'hFE00); - reg [7:0] odata; - wire idata = data; - assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - - always @(negedge clk) - begin - if (decode && rd) - odata <= ram[address[12:0]]; - else if (decode && wr) - ram[address[12:0]] <= data; - end -endmodule - -//module Switches( -// input [15:0] address, -// inout [7:0] data, -// input clk, -// input wr, rd, -// input [7:0] switches, -// output reg [7:0] ledout); - -// wire decode = address == 16'hFF51; -// reg [7:0] odata; -// wire idata = data; -// assign data = (rd && decode) ? odata : 8'bzzzzzzzz; - -// always @(negedge clk) -// begin -// if (decode && rd) -// odata <= switches; -// else if (decode && wr) -// ledout <= data; -// end -//endmodule - -module CoreTop( - input iclk, xtal, - output wire [7:0] leds, - output serio, - output wire [3:0] digits, - output wire [7:0] seven); - - wire clk; - //IBUFG ibuf (.O(clk), .I(iclk)); - - CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); - - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; - - assign leds = iclk?{rd,wr,addr[5:0]}:data[7:0]; - - GBZ80Core core( - .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd)); - - ROM rom( - .address(addr), - .data(data), - .clk(clk), - .wr(wr), - .rd(rd)); - - AddrMon amon( - .addr(addr), - .clk(xtal), - .digit(digits), - .out(seven) - ); - - assign serio = 0; -endmodule - -module TestBench(); - reg clk = 0; - wire [15:0] addr; - wire [7:0] data; - wire wr, rd; - -// wire [7:0] leds; -// wire [7:0] switches; - - always #10 clk <= ~clk; - GBZ80Core core( - .clk(clk), - .busaddress(addr), - .busdata(data), - .buswr(wr), - .busrd(rd)); - - ROM rom( - .clk(clk), - .address(addr), - .data(data), - .wr(wr), - .rd(rd)); - -// InternalRAM ram( -// .address(addr), -// .data(data), -// .clk(clk), -// .wr(wr), -// .rd(rd)); - -// wire serio; -// UART uart( -// .addr(addr), -// .data(data), -// .clk(clk), -// .wr(wr), -// .rd(rd), -// .serial(serio)); - -// Switches sw( -// .clk(clk), -// .address(addr), -// .data(data), -// .wr(wr), -// .rd(rd), -// .switches(switches), -// .leds(leds)); -endmodule