X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/2854e3991ab66f6fb954aba96caf7875d049431e..77ab69d7bb0902e6ebf0994159ed2205f8413e34:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index 9db958f..053df4a 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -79,6 +79,7 @@ `define INSN_BIT 9'b101xxxxxx `define INSN_RES 9'b110xxxxxx `define INSN_SET 9'b111xxxxxx +`define INSN_ADD_HL 9'b000xx1001 `define INSN_cc_NZ 2'b00 `define INSN_cc_Z 2'b01 @@ -152,7 +153,7 @@ module GBZ80Core( inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */ inout [7:0] bus1data, inout bus1wr, bus1rd, - input irq, input [7:0] jaddr, + input irq, output reg irqack, input [7:0] jaddr, output reg [1:0] state); // reg [1:0] state; /* State within this bus cycle (see STATE_*). */ @@ -177,17 +178,21 @@ module GBZ80Core( reg bootstrap_enb; - wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)); /* 0 or 1 depending on which bus */ + wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)) /* 0 or 1 depending on which bus */ + `ifdef isim + || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */ + `endif + ; assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz; assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz; assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz; assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz; assign busdata = (bus == 0) ? bus0data : bus1data; - assign bus0rd = (bus == 0) ? busrd : 1'bz; - assign bus1rd = (bus == 1) ? busrd : 1'bz; - assign bus0wr = (bus == 0) ? buswr : 1'bz; - assign bus1wr = (bus == 1) ? buswr : 1'bz; + assign bus0rd = (bus == 0) ? busrd : 1'b0; + assign bus1rd = (bus == 1) ? busrd : 1'b0; + assign bus0wr = (bus == 0) ? buswr : 1'b0; + assign bus1wr = (bus == 1) ? buswr : 1'b0; reg ie, iedelay; @@ -278,6 +283,7 @@ module GBZ80Core( cycle <= 0; twobyte <= 0; bootstrap_enb <= 1; + irqack <= 0; end always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */ @@ -291,11 +297,16 @@ module GBZ80Core( busaddress <= address; buswr <= wr; busrd <= rd; - if (wr) + if (wr) begin buswdata <= wdata; + if (address == 16'hFF50) + bootstrap_enb <= 0; + end end end `STATE_DECODE: begin /* Make sure this only happens for one clock. */ + buswr <= 0; + busrd <= 0; end endcase @@ -318,7 +329,7 @@ module GBZ80Core( rdata <= busdata; cycle <= 0; end else begin - if (rd) rdata <= busdata; + if (rd) rdata <= busdata; /* Still valid because peripherals are now expected to keep it held valid. */ cycle <= cycle + 1; end if (iedelay) begin @@ -327,13 +338,15 @@ module GBZ80Core( end wr <= 0; rd <= 0; - buswr <= 0; - busrd <= 0; address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened. wdata <= 8'bxxxxxxxx; state <= `STATE_EXECUTE; end `STATE_EXECUTE: begin + `ifdef isim + if (opcode[7:0] === 8'bxxxxxxxx) + $stop; + `endif casex (opcode) `define EXECUTE `include "allinsns.v"