X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/2854e3991ab66f6fb954aba96caf7875d049431e..49c326da841985a8aa48e8544173e5c045c6e0eb:/System.v

diff --git a/System.v b/System.v
index 1872e51..8c4cf1a 100644
--- a/System.v
+++ b/System.v
@@ -6,6 +6,7 @@ module ROM(
 	input clk,
 	input wr, rd);
 
+	reg rdlatch = 0;
 	reg [7:0] odata;
 
 	// synthesis attribute ram_style of rom is block
@@ -13,9 +14,11 @@ module ROM(
 	initial $readmemh("rom.hex", rom);
 
 	wire decode = address[15:13] == 0;
-	always @(posedge clk)
+	always @(posedge clk) begin
+		rdlatch <= rd && decode;
 		odata <= rom[address[10:0]];
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	end
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 
 module BootstrapROM(
@@ -24,12 +27,24 @@ module BootstrapROM(
 	input clk,
 	input wr, rd);
 
-	reg [7:0] brom [255:0];
-	initial $readmemh("bootstrap.hex", brom);
+	reg rdlatch = 0;
+	reg [7:0] addrlatch = 0;
+	reg romno = 0, romnotmp = 0;
+	reg [7:0] brom0 [255:0];
+	reg [7:0] brom1 [255:0];
+	
+	initial $readmemh("fpgaboot.hex", brom0);
+	initial $readmemh("gbboot.hex", brom1);
 
 	wire decode = address[15:8] == 0;
-	wire [7:0] odata = brom[address[7:0]];
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
+	always @(posedge clk) begin
+		rdlatch <= rd && decode;
+		addrlatch <= address[7:0];
+		if (wr && decode) romnotmp <= data[0];
+		if (rd && address == 16'h0000) romno <= romnotmp;	/* Latch when the program restarts. */
+	end
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 
 module MiniRAM(
@@ -41,13 +56,15 @@ module MiniRAM(
 	reg [7:0] ram [127:0];
 	
 	wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+	reg rdlatch = 0;
 	reg [7:0] odata;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 	
 	always @(posedge clk)
 	begin
-		if (decode)	// This has to go this way. The only way XST knows how to do
-		begin				// block ram is chip select, write enable, and always
+		rdlatch <= rd && decode;
+		if (decode)		// This has to go this way. The only way XST knows how to do
+		begin			// block ram is chip select, write enable, and always
 			if (wr)		// reading. "else if rd" does not cut it ...
 				ram[address[6:0]] <= data;
 			odata <= ram[address[6:0]];
@@ -55,6 +72,66 @@ module MiniRAM(
 	end
 endmodule
 
+module CellularRAM(
+	input clk,
+	input [15:0] address,
+	inout [7:0] data,
+	input wr, rd,
+	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+	output wire [22:0] cr_A,
+	inout [15:0] cr_DQ);
+	
+	parameter ADDR_PROGADDRH = 16'hFF60;
+	parameter ADDR_PROGADDRM = 16'hFF61;
+	parameter ADDR_PROGADDRL = 16'hFF62;
+	parameter ADDR_PROGDATA = 16'hFF63;
+	
+	reg rdlatch = 0, wrlatch = 0;
+	reg [15:0] addrlatch = 0;
+	reg [7:0] datalatch = 0;
+	
+	reg [7:0] progaddrh, progaddrm, progaddrl;
+	
+	assign cr_nADV = 0;	/* Addresses are always valid! :D */
+	assign cr_nCE = 0;	/* The chip is enabled */
+	assign cr_nLB = 0;	/* Lower byte is enabled */
+	assign cr_nUB = 0;	/* Upper byte is enabled */
+	assign cr_CRE = 0;	/* Data writes, not config */
+	assign cr_CLK = 0;	/* Clock? I think not! */
+	
+	wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
+	
+	assign cr_nOE = decode ? ~rdlatch : 1;
+	assign cr_nWE = decode ? ~wrlatch : 1;
+	
+	assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
+	assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
+			(addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
+			(addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+			23'b0;
+	
+	reg [7:0] regbuf;
+	
+	always @(posedge clk) begin
+		case (address)
+		ADDR_PROGADDRH: if (wr) progaddrh <= data;
+		ADDR_PROGADDRM: if (wr) progaddrm <= data;
+		ADDR_PROGADDRL: if (wr) progaddrl <= data;
+		endcase
+		rdlatch <= rd;
+		wrlatch <= wr;
+		addrlatch <= address;
+		datalatch <= data;
+	end
+	
+	assign data = (rdlatch && decode) ?
+				(addrlatch == ADDR_PROGADDRH) ? progaddrh :
+				(addrlatch == ADDR_PROGADDRM) ? progaddrm :
+				(addrlatch == ADDR_PROGADDRL) ? progaddrl :
+				cr_DQ
+			: 8'bzzzzzzzz;
+endmodule
+
 module InternalRAM(
 	input [15:0] address,
 	inout [7:0] data,
@@ -64,14 +141,16 @@ module InternalRAM(
 	// synthesis attribute ram_style of ram is block
 	reg [7:0] ram [8191:0];
 	
-	wire decode = address[15:13] == 3'b110;
+	wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);	/* This includes echo RAM. */
 	reg [7:0] odata;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	reg rdlatch = 0;
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 	
 	always @(posedge clk)
 	begin
-		if (decode)	// This has to go this way. The only way XST knows how to do
-		begin				// block ram is chip select, write enable, and always
+		rdlatch <= rd && decode;
+		if (decode)		// This has to go this way. The only way XST knows how to do
+		begin			// block ram is chip select, write enable, and always
 			if (wr)		// reading. "else if rd" does not cut it ...
 				ram[address[12:0]] <= data;
 			odata <= ram[address[12:0]];
@@ -89,10 +168,12 @@ module Switches(
 	
 	wire decode = address == 16'hFF51;
 	reg [7:0] odata;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	reg rdlatch = 0;
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 	
 	always @(posedge clk)
 	begin
+		rdlatch <= rd && decode;
 		if (decode && rd)
 			odata <= switches;
 		else if (decode && wr)
@@ -117,6 +198,9 @@ module CoreTop(
 	output serio,
 	output wire [3:0] digits,
 	output wire [7:0] seven,
+	output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+	output wire [22:0] cr_A,
+	inout [15:0] cr_DQ,
 `endif
 	output wire hs, vs,
 	output wire [2:0] r, g,
@@ -171,12 +255,31 @@ module CoreTop(
 		.wr(wr[1]),
 		.rd(rd[1]));
 	
+`ifdef isim
 	ROM rom(
 		.address(addr[0]),
 		.data(data[0]),
 		.clk(clk),
 		.wr(wr[0]),
 		.rd(rd[0]));
+`else
+	CellularRAM cellram(
+		.address(addr[0]),
+		.data(data[0]),
+		.clk(clk),
+		.wr(wr[0]),
+		.rd(rd[0]),
+		.cr_nADV(cr_nADV),
+		.cr_nCE(cr_nCE),
+		.cr_nOE(cr_nOE),
+		.cr_nWE(cr_nWE),
+		.cr_CRE(cr_CRE),
+		.cr_nLB(cr_nLB),
+		.cr_nUB(cr_nUB),
+		.cr_CLK(cr_CLK),
+		.cr_A(cr_A),
+		.cr_DQ(cr_DQ));
+`endif
 	
 	wire lcdhs, lcdvs, lcdclk;
 	wire [2:0] lcdr, lcdg;