X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/1eefdc8e89a69963b1c1a084fe4ecec844997293..77ab69d7bb0902e6ebf0994159ed2205f8413e34:/System.v diff --git a/System.v b/System.v index 62683d3..68de591 100644 --- a/System.v +++ b/System.v @@ -1,6 +1,6 @@ `timescale 1ns / 1ps -module ROM( +module SimROM( input [15:0] address, inout [7:0] data, input clk, @@ -9,8 +9,7 @@ module ROM( reg rdlatch = 0; reg [7:0] odata; - // synthesis attribute ram_style of rom is block - reg [7:0] rom [1023:0]; + reg [7:0] rom [32767:0]; initial $readmemh("rom.hex", rom); wire decode = address[15:13] == 0; @@ -35,6 +34,10 @@ module BootstrapROM( initial $readmemh("fpgaboot.hex", brom0); initial $readmemh("gbboot.hex", brom1); + +`ifdef isim + initial romno <= 1; +`endif wire decode = address[15:8] == 0; wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch]; @@ -85,6 +88,7 @@ module CellularRAM( parameter ADDR_PROGADDRM = 16'hFF61; parameter ADDR_PROGADDRL = 16'hFF62; parameter ADDR_PROGDATA = 16'hFF63; + parameter ADDR_MBC = 16'hFF64; reg rdlatch = 0, wrlatch = 0; reg [15:0] addrlatch = 0; @@ -94,6 +98,9 @@ module CellularRAM( reg [22:0] progaddr; + reg [7:0] mbc_emul = 8'b00000101; // High bit is whether we're poking flash + // low 7 bits are the MBC that we are emulating + assign cr_nADV = 0; /* Addresses are always valid! :D */ assign cr_nCE = 0; /* The chip is enabled */ assign cr_nLB = 0; /* Lower byte is enabled */ @@ -103,27 +110,44 @@ module CellularRAM( wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA); + reg [3:0] rambank = 0; + reg [8:0] rombank = 1; + assign cr_nOE = decode ? ~rdlatch : 1; - assign cr_nWE = decode ? ~wrlatch : 1; + assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1; assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch}; - assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} : - (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} : + assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} : + (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} : + (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} : (addrlatch == ADDR_PROGDATA) ? progaddr : 23'b0; - reg [7:0] regbuf; - always @(posedge clk) begin case (address) ADDR_PROGADDRH: if (wr) progaddrh <= data; ADDR_PROGADDRM: if (wr) progaddrm <= data; ADDR_PROGADDRL: if (wr) progaddrl <= data; ADDR_PROGDATA: if (rd || wr) begin - progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]}; - {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddr[7:0]} + 23'b1; + progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]}; + {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1; + end + ADDR_MBC: begin + mbc_emul <= data; + rambank <= 0; + rombank <= 1; end endcase + + if (mbc_emul[6:0] == 5) begin + if ((address[15:12] == 4'h2) && wr) + rombank <= {rombank[8], data}; + else if ((address[15:12] == 4'h3) && wr) + rombank <= {data[0], rombank[7:0]}; + else if ((address[15:12] == 4'h4) && wr) + rambank <= data[3:0]; + end + rdlatch <= rd; wrlatch <= wr; addrlatch <= address; @@ -202,11 +226,13 @@ module CoreTop( input [3:0] buttons, output wire [7:0] leds, output serio, + input serin, output wire [3:0] digits, output wire [7:0] seven, output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, output wire [22:0] cr_A, inout [15:0] cr_DQ, + input ps2c, ps2d, `endif output wire hs, vs, output wire [2:0] r, g, @@ -221,6 +247,7 @@ module CoreTop( wire [7:0] leds; wire serio; + wire serin = 1; wire [3:0] digits; wire [7:0] seven; wire [7:0] switches = 8'b0; @@ -230,15 +257,17 @@ module CoreTop( IBUFG iclkbuf(.O(xtalb), .I(xtal)); CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk)); pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk)); + wire [7:0] ps2buttons; `endif wire [15:0] addr [1:0]; wire [7:0] data [1:0]; wire wr [1:0], rd [1:0]; - wire irq, tmrirq, lcdcirq, vblankirq; + wire irq, tmrirq, lcdcirq, vblankirq, btnirq; wire [7:0] jaddr; wire [1:0] state; + wire ack; GBZ80Core core( .clk(clk), @@ -251,6 +280,7 @@ module CoreTop( .bus1wr(wr[1]), .bus1rd(rd[1]), .irq(irq), + .irqack(ack), .jaddr(jaddr), .state(state)); @@ -262,7 +292,7 @@ module CoreTop( .rd(rd[1])); `ifdef isim - ROM rom( + SimROM rom( .address(addr[0]), .data(data[0]), .clk(clk), @@ -319,7 +349,46 @@ module CoreTop( .vgar(r), .vgag(g), .vgab(b)); + + wire [7:0] sleds; +`ifdef isim + assign leds = sleds; +`else + assign leds = sleds | ps2buttons; +`endif + Switches sw( + .clk(clk), + .address(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), + .ledout(sleds), + .switches(switches) + ); +`ifdef isim +`else + PS2Button ps2( + .inclk(ps2c), + .indata(ps2d), + .buttons(ps2buttons) + ); +`endif + + Buttons ass( + .core_clk(clk), + .addr(addr[0]), + .data(data[0]), + .wr(wr[0]), + .rd(rd[0]), + .int(btnirq), + `ifdef isim + .buttons(switches) + `else + .buttons(ps2buttons) + `endif + ); + AddrMon amon( .clk(clk), .addr(addr[0]), @@ -332,23 +401,14 @@ module CoreTop( (state == 2'b10) ? 4'b1000 : 4'b0100) ); - Switches sw( - .clk(clk), - .address(addr[0]), - .data(data[0]), - .wr(wr[0]), - .rd(rd[0]), - .ledout(leds), - .switches(switches) - ); - UART nouart ( /* no u */ .clk(clk), .addr(addr[0]), .data(data[0]), .wr(wr[0]), .rd(rd[0]), - .serial(serio) + .serial(serio), + .serialrx(serin) ); InternalRAM ram( @@ -386,8 +446,9 @@ module CoreTop( .lcdc(lcdcirq), .tovf(tmrirq), .serial(1'b0), - .buttons(1'b0), + .buttons(btnirq), .master(irq), + .ack(ack), .jaddr(jaddr)); Soundcore sound(