X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/1e26cecc7eb53d2765d7a4d7f21ceca81e165409..49c326da841985a8aa48e8544173e5c045c6e0eb:/Uart.v

diff --git a/Uart.v b/Uart.v
index f87005d..07f996a 100644
--- a/Uart.v
+++ b/Uart.v
@@ -1,5 +1,5 @@
 `define IN_CLK 8388608
-`define OUT_CLK 9600
+`define OUT_CLK 57600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50
 
@@ -10,26 +10,27 @@ module UART(
 	input [15:0] addr,
 	inout [7:0] data,
 	output reg serial = 1);
-	
+
+	reg rdlatch = 0;
 	wire decode = (addr == `MMAP_ADDR);
 	
 	wire [7:0] odata;
-	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+	assign data = rdlatch ? odata : 8'bzzzzzzzz;
 
 	reg [7:0] data_stor = 0;
 	reg [15:0] clkdiv = 0;
 	reg have_data = 0;
-	reg data_end = 0;
 	reg [3:0] diqing = 4'b0000;
 	
-	wire new = (wr) && (!have_data) && decode;
+	wire newdata = (wr) && (!have_data) && decode;
 	
 	assign odata = have_data ? 8'b1 : 8'b0;
 
-	always @ (negedge clk)
+	always @ (posedge clk)
 	begin
+		rdlatch <= rd && decode;
 		/* deal with diqing */
-		if(new) begin
+		if(newdata) begin
 			data_stor <= data;
 			have_data <= 1;
 			diqing <= 4'b0000;
@@ -53,7 +54,7 @@ module UART(
 		end
 
 		/* deal with clkdiv */
-		if((new && !have_data) || clkdiv == `CLK_DIV)
+		if((newdata && !have_data) || clkdiv == `CLK_DIV)
 			clkdiv <= 0;
 		else
 			clkdiv <= clkdiv + 1;