X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/179b434745a7b2da871d69c201dd1bda3e445f41..c279b66691509cfc4445a568dab29a3282f03f3f:/System.v diff --git a/System.v b/System.v index 00ee4ec..caa6ae3 100644 --- a/System.v +++ b/System.v @@ -6,22 +6,45 @@ module ROM( input clk, input wr, rd); - reg [7:0] rom [2047:0]; + reg [7:0] rom [1023:0]; initial $readmemh("rom.hex", rom); wire decode = address[15:13] == 0; - wire [7:0] odata = rom[address[11:0]]; + wire [7:0] odata = rom[address[10:0]]; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; //assign data = rd ? odata : 8'bzzzzzzzz; endmodule +module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */ + input [15:0] address, + inout [7:0] data, + input clk, + input wr, rd); + + reg [7:0] ram [127:0]; + + wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE); + reg [7:0] odata; + assign data = (rd && decode) ? odata : 8'bzzzzzzzz; + + always @(negedge clk) + begin + if (decode) // This has to go this way. The only way XST knows how to do + begin // block ram is chip select, write enable, and always + if (wr) // reading. "else if rd" does not cut it ... + ram[address[6:0]] <= data; + odata <= ram[address[6:0]]; + end + end +endmodule + module InternalRAM( input [15:0] address, inout [7:0] data, input clk, input wr, rd); - // synthesis attribute ram_style of reg is block + // synthesis attribute ram_style of ram is block reg [7:0] ram [8191:0]; wire decode = address[15:13] == 3'b110; @@ -67,20 +90,21 @@ module CoreTop( output wire [7:0] leds, output serio, output wire [3:0] digits, - output wire [7:0] seven); + output wire [7:0] seven, + output wire hs, vs, + output wire [2:0] r, g, + output wire [1:0] b); - wire clk; - CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk)); + wire xtalb, clk, vgaclk; + IBUFG iclkbuf(.O(xtalb), .I(xtal)); + CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk)); + pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk)); - wire cclk; -// IBUFG ibuf (.O(cclk), .I(switches[0] & clk)); - assign cclk = clk; - wire [15:0] addr; wire [7:0] data; wire wr, rd; - wire irq, tmrirq; + wire irq, tmrirq, lcdcirq, vblankirq; wire [7:0] jaddr; wire [1:0] state; @@ -101,6 +125,39 @@ module CoreTop( .wr(wr), .rd(rd)); + wire lcdhs, lcdvs, lcdclk; + wire [2:0] lcdr, lcdg; + wire [1:0] lcdb; + + LCDC lcdc( + .addr(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd), + .lcdcirq(lcdcirq), + .vblankirq(vblankirq), + .lcdclk(lcdclk), + .lcdhs(lcdhs), + .lcdvs(lcdvs), + .lcdr(lcdr), + .lcdg(lcdg), + .lcdb(lcdb)); + + Framebuffer fb( + .lcdclk(lcdclk), + .lcdhs(lcdhs), + .lcdvs(lcdvs), + .lcdr(lcdr), + .lcdg(lcdg), + .lcdb(lcdb), + .vgaclk(vgaclk), + .vgahs(hs), + .vgavs(vs), + .vgar(r), + .vgag(g), + .vgab(b)); + AddrMon amon( .addr(addr), .clk(clk), @@ -120,7 +177,7 @@ module CoreTop( .wr(wr), .rd(rd), .ledout(leds), - .switches({switches[7:1],1'b0}) + .switches(switches) ); UART nouart ( /* no u */ @@ -139,6 +196,14 @@ module CoreTop( .wr(wr), .rd(rd) ); + + MiniRAM mram( + .address(addr), + .data(data), + .clk(clk), + .wr(wr), + .rd(rd) + ); Timer tmr( .clk(clk), @@ -155,8 +220,8 @@ module CoreTop( .wr(wr), .addr(addr), .data(data), - .vblank(0), - .lcdc(0), + .vblank(vblankirq), + .lcdc(lcdcirq), .tovf(tmrirq), .serial(0), .buttons(0),