X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/06ad3a30038ac8ca45dd7b0c34213c0c8335c17c..f9000d73c8971e2e6323122efb06bcfd846b5d62:/System.v

diff --git a/System.v b/System.v
index a5fee66..5b0fb3c 100644
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
 	
 	wire decode = address[15:13] == 3'b110;
 	reg [7:0] odata;
-	wire idata = data;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
 	always @(negedge clk)
@@ -46,7 +45,7 @@ module Switches(
 	input clk,
 	input wr, rd,
 	input [7:0] switches,
-	output reg [7:0] ledout);
+	output reg [7:0] ledout = 0);
 	
 	wire decode = address == 16'hFF51;
 	reg [7:0] odata;
@@ -72,17 +71,24 @@ module CoreTop(
 	
 	wire clk;	
 	CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
+	
 	wire [15:0] addr;	
 	wire [7:0] data;
 	wire wr, rd;
-
+	
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	wire [1:0] state;
+	
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
-		.busrd(rd));
+		.busrd(rd),
+		.irq(irq),
+		.jaddr(jaddr),
+		.state(state));
 	
 	ROM rom(
 		.address(addr),
@@ -92,12 +98,16 @@ module CoreTop(
 		.rd(rd));
 	
 	AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-	 .freeze(buttons[0])
-    );
+		.addr(addr), 
+		.clk(clk), 
+		.digit(digits), 
+		.out(seven),
+		.freeze(buttons[0]),
+		.periods(
+			(state == 2'b00) ? 4'b0010 :
+			(state == 2'b01) ? 4'b0001 :
+			(state == 2'b10) ? 4'b1000 :
+			                   4'b0100) );
 	 
 	Switches sw(
 		.address(addr),
@@ -110,30 +120,30 @@ module CoreTop(
 		);
 
 	UART nouart (	/* no u */
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+		.clk(clk), 
+		.wr(wr), 
+		.rd(rd), 
+		.addr(addr), 
+		.data(data), 
+		.serial(serio)
+		);
 
-  InternalRAM ram(
+	InternalRAM ram(
 		.address(addr),
 		.data(data),
 		.clk(clk),
 		.wr(wr),
-		.rd(rd));
+		.rd(rd)
+		);
 
-	wire irq, tmrirq;
-	wire [7:0] jaddr;
 	Timer tmr(
 		.clk(clk),
 		.wr(wr),
 		.rd(rd),
 		.addr(addr),
 		.data(data),
-		.irq(tmrirq));
+		.irq(tmrirq)
+		);
 	
 	Interrupt intr(
 		.clk(clk),
@@ -151,21 +161,26 @@ module CoreTop(
 endmodule
 
 module TestBench();
-	reg clk = 0;
+	reg clk = 1;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
 	
-//	wire [7:0] leds;
-//	wire [7:0] switches;
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	
+	wire [7:0] leds;
+	wire [7:0] switches;
 	
-	always #10 clk <= ~clk;
+	always #62 clk <= ~clk;
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
-		.busrd(rd));
+		.busrd(rd),
+		.irq(irq),
+		.jaddr(jaddr));
 	
 	ROM rom(
 		.clk(clk),
@@ -190,8 +205,6 @@ module TestBench();
 		.rd(rd),
 		.serial(serio));
 	
-	wire irq, tmrirq;
-	wire [7:0] jaddr;
 	Timer tmr(
 		.clk(clk),
 		.wr(wr),
@@ -214,12 +227,12 @@ module TestBench();
 		.master(irq),
 		.jaddr(jaddr));
 	
-//	Switches sw(
-//		.clk(clk),
-//		.address(addr),
-//		.data(data),
-//		.wr(wr),
-//		.rd(rd),
-//		.switches(switches),
-//		.leds(leds));
+	Switches sw(
+		.clk(clk),
+		.address(addr),
+		.data(data),
+		.wr(wr),
+		.rd(rd),
+		.switches(switches),
+		.ledout(leds));
 endmodule