X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/06ad3a30038ac8ca45dd7b0c34213c0c8335c17c..5bac4cf0a60acac6826eb3215e1526d48ba8f7ac:/System.v diff --git a/System.v b/System.v index a5fee66..0afc090 100644 --- a/System.v +++ b/System.v @@ -26,7 +26,6 @@ module InternalRAM( wire decode = address[15:13] == 3'b110; reg [7:0] odata; - wire idata = data; assign data = (rd && decode) ? odata : 8'bzzzzzzzz; always @(negedge clk) @@ -46,7 +45,7 @@ module Switches( input clk, input wr, rd, input [7:0] switches, - output reg [7:0] ledout); + output reg [7:0] ledout = 0); wire decode = address == 16'hFF51; reg [7:0] odata; @@ -76,13 +75,18 @@ module CoreTop( wire [15:0] addr; wire [7:0] data; wire wr, rd; + + wire irq, tmrirq; + wire [7:0] jaddr; GBZ80Core core( .clk(clk), .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr)); ROM rom( .address(addr), @@ -92,12 +96,11 @@ module CoreTop( .rd(rd)); AddrMon amon( - .addr(addr), - .clk(clk), - .digit(digits), - .out(seven), - .freeze(buttons[0]) - ); + .addr(addr), + .clk(clk), + .digit(digits), + .out(seven), + .freeze(buttons[0])); Switches sw( .address(addr), @@ -110,30 +113,30 @@ module CoreTop( ); UART nouart ( /* no u */ - .clk(clk), - .wr(wr), - .rd(rd), - .addr(addr), - .data(data), - .serial(serio) - ); + .clk(clk), + .wr(wr), + .rd(rd), + .addr(addr), + .data(data), + .serial(serio) + ); - InternalRAM ram( + InternalRAM ram( .address(addr), .data(data), .clk(clk), .wr(wr), - .rd(rd)); + .rd(rd) + ); - wire irq, tmrirq; - wire [7:0] jaddr; Timer tmr( .clk(clk), .wr(wr), .rd(rd), .addr(addr), .data(data), - .irq(tmrirq)); + .irq(tmrirq) + ); Interrupt intr( .clk(clk), @@ -151,13 +154,16 @@ module CoreTop( endmodule module TestBench(); - reg clk = 0; + reg clk = 1; wire [15:0] addr; wire [7:0] data; wire wr, rd; -// wire [7:0] leds; -// wire [7:0] switches; + wire irq, tmrirq; + wire [7:0] jaddr; + + wire [7:0] leds; + wire [7:0] switches; always #10 clk <= ~clk; GBZ80Core core( @@ -165,7 +171,9 @@ module TestBench(); .busaddress(addr), .busdata(data), .buswr(wr), - .busrd(rd)); + .busrd(rd), + .irq(irq), + .jaddr(jaddr)); ROM rom( .clk(clk), @@ -190,8 +198,6 @@ module TestBench(); .rd(rd), .serial(serio)); - wire irq, tmrirq; - wire [7:0] jaddr; Timer tmr( .clk(clk), .wr(wr), @@ -214,12 +220,12 @@ module TestBench(); .master(irq), .jaddr(jaddr)); -// Switches sw( -// .clk(clk), -// .address(addr), -// .data(data), -// .wr(wr), -// .rd(rd), -// .switches(switches), -// .leds(leds)); + Switches sw( + .clk(clk), + .address(addr), + .data(data), + .wr(wr), + .rd(rd), + .switches(switches), + .ledout(leds)); endmodule