X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/06ad3a30038ac8ca45dd7b0c34213c0c8335c17c..318331120b0bd48a06902e70a63b4f536a85de5f:/System.v

diff --git a/System.v b/System.v
index a5fee66..7319ebf 100644
--- a/System.v
+++ b/System.v
@@ -76,13 +76,18 @@ module CoreTop(
 	wire [15:0] addr;	
 	wire [7:0] data;
 	wire wr, rd;
+	
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
 
 	GBZ80Core core(
 		.clk(clk),
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
-		.busrd(rd));
+		.busrd(rd),
+		.irq(irq),
+		.jaddr(jaddr));
 	
 	ROM rom(
 		.address(addr),
@@ -125,8 +130,6 @@ module CoreTop(
 		.wr(wr),
 		.rd(rd));
 
-	wire irq, tmrirq;
-	wire [7:0] jaddr;
 	Timer tmr(
 		.clk(clk),
 		.wr(wr),
@@ -151,11 +154,14 @@ module CoreTop(
 endmodule
 
 module TestBench();
-	reg clk = 0;
+	reg clk = 1;
 	wire [15:0] addr;
 	wire [7:0] data;
 	wire wr, rd;
 	
+	wire irq, tmrirq;
+	wire [7:0] jaddr;
+	
 //	wire [7:0] leds;
 //	wire [7:0] switches;
 	
@@ -165,7 +171,9 @@ module TestBench();
 		.busaddress(addr),
 		.busdata(data),
 		.buswr(wr),
-		.busrd(rd));
+		.busrd(rd),
+		.irq(irq),
+		.jaddr(jaddr));
 	
 	ROM rom(
 		.clk(clk),
@@ -190,8 +198,6 @@ module TestBench();
 		.rd(rd),
 		.serial(serio));
 	
-	wire irq, tmrirq;
-	wire [7:0] jaddr;
 	Timer tmr(
 		.clk(clk),
 		.wr(wr),