X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/06ad3a30038ac8ca45dd7b0c34213c0c8335c17c..298e8085b4f8f70121204fa4aed3a188034f6879:/Interrupt.v

diff --git a/Interrupt.v b/Interrupt.v
index 4e3d17d..2686146 100644
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -17,12 +17,15 @@ module Interrupt(
 
 	wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
 	reg [7:0] imask = 16'hFFFF;
-	reg [7:0] ihold = 0;
+	reg [7:0] ihold = 8'b0;
 	wire [7:0] imasked = ihold & imask;
+	
+	reg rdlatch = 0;
+	reg [15:0] addrlatch = 0;
 
-	assign data = rd ?
-	                 (addr == `ADDR_IF) ? ihold :
-	                 (addr == `ADDR_IE) ? imask :
+	assign data = rdlatch ?
+	                 (addrlatch == `ADDR_IF) ? ihold :
+	                 (addrlatch == `ADDR_IE) ? imask :
 	                 8'bzzzzzzzz :
 		      8'bzzzzzzzz;
 
@@ -34,17 +37,19 @@ module Interrupt(
 		       imasked[3] ? 8'h58 :
 		       imasked[4] ? 8'h60 : 8'h00;
 
-	always @ (negedge clk)
+	always @(posedge clk)
 	begin
-		if (wr) begin
+		if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
 			case(addr)
 			`ADDR_IF : ihold <= iflag | data;
-			`ADDR_IE : imask <= data;
+			`ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
 			endcase
 			
 		end
 		else
 			ihold <= ihold | iflag;
+		rdlatch <= rd;
+		addrlatch <= addr;
 	end
 
 endmodule