X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/01878f5fdca9d08e4cf7ceed7f5a39f4df602de4..aebd667080a34f41a93e3cf79a6c91cb2e6aaa37:/Soundcore.v

diff --git a/Soundcore.v b/Soundcore.v
index b2c4d35..70c4db1 100644
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -12,9 +12,9 @@ module Soundcore(
 	output reg snd_data_r
 	);
 
-	reg [7:0] nr50,nr51,nr52;
-	reg [3:0] pwmcnt;
-	reg [4:0] cntclk;
+	reg [7:0] nr50 = 8'h00, nr51 = 8'h00, nr52 = 8'hF0;
+	reg [3:0] pwmcnt = 4'b0000;
+	reg [4:0] cntclk = 5'b00000;
 	reg [13:0] lenclk;
 	wire [3:0] sndout1,sndout2,sndout3,sndout4;
 	wire [3:0] right_snd =
@@ -29,14 +29,19 @@ module Soundcore(
 		(nr51[7] ? sndout4 : 4'b0);
 	assign sndout3 = 0;
 	assign sndout4 = 0;
-
-	assign data = rd ?
-	                 addr == `ADDR_NR50 ? nr50 :
-	                 addr == `ADDR_NR51 ? nr51 :
-	                 addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
+	
+	reg rdlatch;
+	reg [15:0] addrlatch;
+	
+	assign data = rdlatch ?
+	                 addrlatch == `ADDR_NR50 ? nr50 :
+	                 addrlatch == `ADDR_NR51 ? nr51 :
+	                 addrlatch == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
 		      : 8'bzzzzzzzz;
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
+		rdlatch <= rd;
+		addrlatch <= addr;
 		if(wr) begin
 			case(addr)
 			`ADDR_NR50: nr50 <= data;
@@ -47,8 +52,8 @@ module Soundcore(
 		cntclk <= cntclk + 1;
 		lenclk <= lenclk + 1;
 		pwmcnt <= pwmcnt + 1; 
-		snd_data_l <= (pwmcnt <= left_snd) ? nr50[7] : 0;
-		snd_data_r <= (pwmcnt <= right_snd) ? nr50[3] : 0;
+		snd_data_l <= (pwmcnt <= left_snd) ? 1 : 0;
+		snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
 	end
 
 	Sound1 s1(