X-Git-Url: http://git.joshuawise.com/fpgaboy.git/blobdiff_plain/00e30b4dd08f216cc9fe89295f575b9b7d0622b5..abae5818eeec14c040361b5181ff1a31cad79868:/GBZ80Core.v diff --git a/GBZ80Core.v b/GBZ80Core.v index 1d06b12..c0c2b26 100644 --- a/GBZ80Core.v +++ b/GBZ80Core.v @@ -31,6 +31,12 @@ `define INSN_PUSH_reg 8'b11xx0101 `define INSN_POP_reg 8'b11xx0001 `define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A +`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A +`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy +`define INSN_NOP 8'b00000000 +`define INSN_RST 8'b11xxx111 +`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET + `define INSN_reg_A 3'b111 `define INSN_reg_B 3'b000 `define INSN_reg_C 3'b001 @@ -47,6 +53,15 @@ `define INSN_stack_BC 2'b00 `define INSN_stack_DE 2'b01 `define INSN_stack_HL 2'b10 +`define INSN_alu_ADD 3'b000 +`define INSN_alu_ADC 3'b001 +`define INSN_alu_SUB 3'b010 +`define INSN_alu_SBC 3'b011 +`define INSN_alu_AND 3'b100 +`define INSN_alu_XOR 3'b101 +`define INSN_alu_OR 3'b110 +`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP? + module GBZ80Core( input clk, output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */ @@ -70,6 +85,8 @@ module GBZ80Core( reg [7:0] buswdata; assign busdata = buswr ? buswdata : 8'bzzzzzzzz; + reg ie = 0; + initial begin registers[ 0] <= 0; registers[ 1] <= 0; @@ -275,7 +292,7 @@ module GBZ80Core( rd <= 1; end else begin wr <= 1; - wdata <= {8'hFF,registers[`REG_A]}; + wdata <= registers[`REG_A]; end end 1: begin @@ -284,6 +301,86 @@ module GBZ80Core( end endcase end + `INSN_LDx_AHL: begin + case (cycle) + 0: begin + address <= {registers[`REG_H],registers[`REG_L]}; + if (opcode[3]) begin // LDx A, (HL) + rd <= 1; + end else begin + wr <= 1; + wdata <= registers[`REG_A]; + end + end + 1: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + endcase + end + `INSN_ALU8: begin + if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin + // fffffffff fuck your shit, read from (HL) :( + rd <= 1; + address <= {registers[`REG_H], registers[`REG_L]}; + end else begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + case (opcode[2:0]) + `INSN_reg_A: begin tmp <= registers[`REG_A]; end + `INSN_reg_B: begin tmp <= registers[`REG_B]; end + `INSN_reg_C: begin tmp <= registers[`REG_C]; end + `INSN_reg_D: begin tmp <= registers[`REG_D]; end + `INSN_reg_E: begin tmp <= registers[`REG_E]; end + `INSN_reg_H: begin tmp <= registers[`REG_H]; end + `INSN_reg_L: begin tmp <= registers[`REG_L]; end + `INSN_reg_dHL: begin tmp <= rdata; end + endcase + end + end + `INSN_NOP: begin + `EXEC_NEWCYCLE; + `EXEC_INC_PC; + end + `INSN_RST: begin + case (cycle) + 0: begin + `EXEC_INC_PC; // This goes FIRST + end + 1: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-1; + wdata <= registers[`REG_PCH]; + end + 2: begin + wr <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}-2; + wdata <= registers[`REG_PCL]; + end + 3: begin + `EXEC_NEWCYCLE; + {registers[`REG_PCH],registers[`REG_PCL]} <= + {10'b0,opcode[5:3],3'b0}; + end + endcase + end + `INSN_RET: begin + case (cycle) + 0: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]}; + end + 1: begin + rd <= 1; + address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1; + end + 2: begin /* twiddle thumbs */ end + 3: begin + `EXEC_NEWCYCLE; + // do NOT increment PC! + end + endcase + end default: $stop; endcase @@ -434,6 +531,113 @@ module GBZ80Core( end endcase end + `INSN_LDx_AHL: begin + case (cycle) + 0: cycle <= 1; + 1: begin + cycle <= 0; + if (opcode[3]) + registers[`REG_A] <= rdata; + {registers[`REG_H],registers[`REG_L]} <= + opcode[4] ? // if set, LDD, else LDI + ({registers[`REG_H],registers[`REG_L]} - 1) : + ({registers[`REG_H],registers[`REG_L]} + 1); + end + endcase + end + `INSN_ALU8: begin + if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin + /* Sit on our asses. */ + cycle <= 1; + end else begin /* Actually do the computation! */ + case (opcode[5:3]) + `INSN_alu_ADD: begin + registers[`REG_A] <= + registers[`REG_A] + tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0, + /* N */ 1'b0, + /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end + `INSN_alu_ADC: begin + registers[`REG_A] <= + registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0, + /* N */ 1'b0, + /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0, + /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0, + registers[`REG_F][3:0] + }; + end + `INSN_alu_AND: begin + registers[`REG_A] <= + registers[`REG_A] & tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0, + 3'b010, + registers[`REG_F][3:0] + }; + end + `INSN_alu_OR: begin + registers[`REG_A] <= + registers[`REG_A] | tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0, + 3'b000, + registers[`REG_F][3:0] + }; + end + `INSN_alu_XOR: begin + registers[`REG_A] <= + registers[`REG_A] ^ tmp; + registers[`REG_F] <= + { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0, + 3'b000, + registers[`REG_F][3:0] + }; + end + default: + $stop; + endcase + end + end + `INSN_NOP: begin /* NOP! */ end + `INSN_RST: begin + case (cycle) + 0: cycle <= 1; + 1: cycle <= 2; + 2: cycle <= 3; + 3: begin + cycle <= 0; + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]}-2; + end + endcase + end + `INSN_RET: begin + case (cycle) + 0: cycle <= 1; + 1: begin + cycle <= 2; + registers[`REG_PCL] <= rdata; + end + 2: begin + cycle <= 3; + registers[`REG_PCH] <= rdata; + end + 3: begin + cycle <= 0; + {registers[`REG_SPH],registers[`REG_SPL]} <= + {registers[`REG_SPH],registers[`REG_SPL]} + 2; + if (opcode[4]) /* RETI */ + ie <= 1; + end + endcase + end endcase state <= `STATE_FETCH; end