Poke the LEDs. YOUR MOM WAS TOO WIDE

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 033e4b180bca090e52953022b3b5f94b985d9ec0..8b8d61344f712e4c39cfae009bf71969f67039a9 100644 (file)
--- a/System.v
+++ b/System.v
@@ -21,19 +21,22 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
+       // synthesis attribute ram_style of reg is block
        reg [7:0] ram [8191:0];
        
-       wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
+       wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
-               if (decode && rd)
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
-               else if (decode && wr)
-                       ram[address[12:0]] <= data;
+               end
        end
 endmodule
 
@@ -67,9 +70,7 @@ module CoreTop(
        output wire [3:0] digits,
        output wire [7:0] seven);
        
-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
-       
+       wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
        wire [15:0] addr;       
@@ -108,7 +109,7 @@ module CoreTop(
                .switches(switches)
                );
 
-       UART nouart (
+       UART nouart (   /* no u */
     .clk(clk), 
     .wr(wr), 
     .rd(rd), 
@@ -123,10 +124,34 @@ module CoreTop(
                .clk(clk),
                .wr(wr),
                .rd(rd));
+
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
 endmodule
 
 module TestBench();
-       reg clk = 0;
+       reg clk = 1;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
@@ -165,6 +190,30 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
+       
 //     Switches sw(
 //             .clk(clk),
 //             .address(addr),