Compiles

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index dbcfaa43f65daf5c8a8b8db69773a9a1e8624603..dc70cc0d9d7a49cab58aec6a2ba9a8ae05e4070e 100644 (file)
--- a/System.v
+++ b/System.v
@@ -15,6 +15,29 @@ module ROM(
        //assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
+module MiniRAM(                        /* XXX will need to go INSIDE the CPU for when we do DMA */
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+       
+       reg [7:0] ram [127:0];
+       
+       wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+       reg [7:0] odata;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+       always @(negedge clk)
+       begin
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[6:0]] <= data;
+                       odata <= ram[address[6:0]];
+               end
+       end
+endmodule
+
 module InternalRAM(
        input [15:0] address,
        inout [7:0] data,
@@ -70,7 +93,8 @@ module CoreTop(
        output wire [7:0] seven,
        output wire hs, vs,
        output wire [2:0] r, g,
-       output wire [1:0] b);
+       output wire [1:0] b,
+       output wire soundl, soundr);
        
        wire xtalb, clk, vgaclk;
        IBUFG iclkbuf(.O(xtalb), .I(xtal));
@@ -173,6 +197,14 @@ module CoreTop(
                .wr(wr),
                .rd(rd)
                );
+       
+       MiniRAM mram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd)
+               );
 
        Timer tmr(
                .clk(clk),
@@ -196,6 +228,15 @@ module CoreTop(
                .buttons(0),
                .master(irq),
                .jaddr(jaddr));
+       
+       Soundcore sound(
+               .core_clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .snd_data_l(soundl),
+               .snd_data_r(soundr));
 endmodule
 
 module TestBench();