Readd .keep

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 5b0fb3cc45f05c81f58e96f7263b386e4eaf1619..dbcfaa43f65daf5c8a8b8db69773a9a1e8624603 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,11 +6,11 @@ module ROM(
        input clk,
        input wr, rd);
 
-       reg [7:0] rom [2047:0];
+       reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
-       wire [7:0] odata = rom[address[11:0]];
+       wire [7:0] odata = rom[address[10:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        //assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
@@ -21,7 +21,7 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
-       // synthesis attribute ram_style of reg is block
+       // synthesis attribute ram_style of ram is block
        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
@@ -67,16 +67,21 @@ module CoreTop(
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
-       output wire [7:0] seven);
+       output wire [7:0] seven,
+       output wire hs, vs,
+       output wire [2:0] r, g,
+       output wire [1:0] b);
        
-       wire clk;       
-       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
+       wire xtalb, clk, vgaclk;
+       IBUFG iclkbuf(.O(xtalb), .I(xtal));
+       CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+       pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
        
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        
-       wire irq, tmrirq;
+       wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;
        wire [1:0] state;
        
@@ -97,6 +102,39 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
        
+       wire lcdhs, lcdvs, lcdclk;
+       wire [2:0] lcdr, lcdg;
+       wire [1:0] lcdb;
+       
+       LCDC lcdc(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .lcdcirq(lcdcirq),
+               .vblankirq(vblankirq),
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb));
+       
+       Framebuffer fb(
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb),
+               .vgaclk(vgaclk),
+               .vgahs(hs),
+               .vgavs(vs),
+               .vgar(r),
+               .vgag(g),
+               .vgab(b));
+       
        AddrMon amon(
                .addr(addr), 
                .clk(clk), 
@@ -151,8 +189,8 @@ module CoreTop(
                .wr(wr),
                .addr(addr),
                .data(data),
-               .vblank(0),
-               .lcdc(0),
+               .vblank(vblankirq),
+               .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(0),
                .buttons(0),