IP

[fpgaboy.git] / Ethernet.v

diff --git a/Ethernet.v b/Ethernet.v
index d96158534dc52154ceda219ce7d2c66db4934d0d..56123c09d251530f11b4858277a9c90805f9486e 100644 (file)
--- a/Ethernet.v
+++ b/Ethernet.v
@@ -40,7 +40,7 @@ module Ethernet (
        EthModRam txram(
                .wdata(data),
                .waddr(txwraddr),
        EthModRam txram(
                .wdata(data),
                .waddr(txwraddr),

-               .wr(wr && state == 2'b10 && addr == `ADDR_ETH),
+               .wr(wr && txstate == 2'b10 && addr == `ADDR_ETH),

                .wrclk(clk),
                .rdata(txhwdata),
                .raddr(txhwaddr),
                .wrclk(clk),
                .rdata(txhwdata),
                .raddr(txhwaddr),


@@ -82,7 +82,7 @@ module Ethernet (
                rdlatch <= rd;
                
                if (rd && addr == `ADDR_ETH_STATUS)
                rdlatch <= rd;
                
                if (rd && addr == `ADDR_ETH_STATUS)

-                       odata <= {state,4'b0,rxpktrdy,txbusy};
+                       odata <= {txstate,4'b0,rxpktrdy,txbusy};

                else if (wr && addr == `ADDR_ETH_STATUS) begin          /* Reset the state machines. */
                        rxstate <= 2'b00;
                        txstate <= 2'b00;
                else if (wr && addr == `ADDR_ETH_STATUS) begin          /* Reset the state machines. */
                        rxstate <= 2'b00;
                        txstate <= 2'b00;


@@ -259,16 +259,18 @@ module EnetRX(
        reg [2:0] transition_timeout;
        always @(posedge rxclk) if(in_data[2]^in_data[1]) transition_timeout<=0; else if(~&cnt) transition_timeout<=transition_timeout+1;
        always @(posedge rxclk) end_of_Ethernet_frame <= &transition_timeout;
        reg [2:0] transition_timeout;
        always @(posedge rxclk) if(in_data[2]^in_data[1]) transition_timeout<=0; else if(~&cnt) transition_timeout<=transition_timeout+1;
        always @(posedge rxclk) end_of_Ethernet_frame <= &transition_timeout;

+       reg [11:0] iaddr;

        
        /////////////////////////////////////////////////
        always @(posedge rxclk)
                if (new_byte_available && !pktrdy) begin
                        odata <= data;
        
        /////////////////////////////////////////////////
        always @(posedge rxclk)
                if (new_byte_available && !pktrdy) begin
                        odata <= data;

-                       oaddr <= oaddr + 1;
+                       oaddr <= iaddr;
+                       iaddr <= iaddr + 1;

                        wr <= 1;
                        wr <= 1;

-               end else if (end_of_Ethernet_frame && (oaddr > 1)) begin
-                       olength <= oaddr;
-                       oaddr <= 0;
+               end else if (end_of_Ethernet_frame && (iaddr > 1)) begin
+                       olength <= iaddr;
+                       iaddr <= 0;

                        wr <= 0;
                        pktrdy <= 1;
                end else if (pktclear) begin
                        wr <= 0;
                        pktrdy <= 1;
                end else if (pktclear) begin