New ethernet code

[fpgaboy.git] / Ethernet.v

diff --git a/Ethernet.v b/Ethernet.v
index d96158534dc52154ceda219ce7d2c66db4934d0d..bd3fdc734dcc87faacefedec32e1936babc96827 100644 (file)
--- a/Ethernet.v
+++ b/Ethernet.v
@@ -259,16 +259,18 @@ module EnetRX(
        reg [2:0] transition_timeout;
        always @(posedge rxclk) if(in_data[2]^in_data[1]) transition_timeout<=0; else if(~&cnt) transition_timeout<=transition_timeout+1;
        always @(posedge rxclk) end_of_Ethernet_frame <= &transition_timeout;
+       reg [11:0] iaddr;
        
        /////////////////////////////////////////////////
        always @(posedge rxclk)
                if (new_byte_available && !pktrdy) begin
                        odata <= data;
-                       oaddr <= oaddr + 1;
+                       oaddr <= iaddr;
+                       iaddr <= iaddr + 1;
                        wr <= 1;
-               end else if (end_of_Ethernet_frame && (oaddr > 1)) begin
-                       olength <= oaddr;
-                       oaddr <= 0;
+               end else if (end_of_Ethernet_frame && (iaddr > 1)) begin
+                       olength <= iaddr;
+                       iaddr <= 0;
                        wr <= 0;
                        pktrdy <= 1;
                end else if (pktclear) begin