Add cut 1 of a cellram module

[fpgaboy.git] / opcodes

diff --git a/opcodes b/opcodes
index 6a54b02f6794abaf3082b92e9a0a29809ad51043..09f68fbce78aa2756211461a9e610ad3ede999ba 100644 (file)
--- a/opcodes
+++ b/opcodes
@@ -7,14 +7,10 @@ imm16 = 16-bit immediate value
 8m8   = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
 
 bits         insn                 notes
 8m8   = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
 
 bits         insn                 notes

-0000 0010    LD    (BC), A

 0000 1000    LD    16m16,SP      loads SP
 0000 1001    ADD   HL,   BC
 0000 1000    LD    16m16,SP      loads SP
 0000 1001    ADD   HL,   BC

-0000 1010    LD    A,    (BC) 

 0001 0000    STOP
 0001 0000    STOP

-0001 0010    LD    (DE), A

 0001 1001    ADD   HL,   DE
 0001 1001    ADD   HL,   DE

-0001 1010    LD    A,    (DE)

 0010 1001    ADD   HL,   HL
 0011 1001    ADD   HL,   SP
 0111 0110    HALT                 Danger! Helvetica!
 0010 1001    ADD   HL,   HL
 0011 1001    ADD   HL,   SP
 0111 0110    HALT                 Danger! Helvetica!


@@ -99,15 +95,6 @@ bits                   insn               notes
 1100 1011 0011 0110    SWAP  (HL)
 1100 1011 0011 0111    SWAP  A
 
 1100 1011 0011 0110    SWAP  (HL)
 1100 1011 0011 0111    SWAP  A
 

-1100 1011 0100 0000    BIT   imm3, B      test bit specified by imm3
-1100 1011 0100 0001    BIT   imm3, C
-1100 1011 0100 0010    BIT   imm3, D
-1100 1011 0100 0011    BIT   imm3, E
-1100 1011 0100 0100    BIT   imm3, H
-1100 1011 0100 0101    BIT   imm3, L
-1100 1011 0100 0110    BIT   imm3, (HL)
-1100 1011 0100 0111    BIT   imm3, A
-

 1100 1011 1000 0000    RES   imm3, B      reset bit specified by imm3
 1100 1011 1000 0001    RES   imm3, C
 1100 1011 1000 0010    RES   imm3, D
 1100 1011 1000 0000    RES   imm3, B      reset bit specified by imm3
 1100 1011 1000 0001    RES   imm3, C
 1100 1011 1000 0010    RES   imm3, D