Start refactoring instructions.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa..5d4fbedf2acadf14bd48a28dfb153570ed63a1cf 100644 (file)
--- a/System.v
+++ b/System.v
@@ -46,7 +46,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
@@ -162,8 +162,8 @@ module TestBench();
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire [7:0] leds;
+       wire [7:0] switches;
        
        always #10 clk <= ~clk;
        GBZ80Core core(
@@ -220,12 +220,12 @@ module TestBench();
                .master(irq),
                .jaddr(jaddr));
        
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));
 endmodule