module GBZ80Core(
input clk,
- output reg [15:0] busaddress = 0, /* BUS_* is latched on STATE_FETCH. */
+ output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
inout [7:0] busdata,
- output reg buswr = 0, output reg busrd = 0,
+ output reg buswr, output reg busrd,
input irq, input [7:0] jaddr);
- reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */
- reg [2:0] cycle = 0; /* Cycle for instructions. */
+ reg [1:0] state; /* State within this bus cycle (see STATE_*). */
+ reg [2:0] cycle; /* Cycle for instructions. */
reg [7:0] registers[11:0];
reg [7:0] opcode; /* Opcode from the current machine cycle. */
reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
- reg rd = 1, wr = 0, newcycle = 1;
+ reg rd, wr, newcycle;
reg [7:0] tmp, tmp2; /* Generic temporary regs. */
reg [7:0] buswdata;
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
- reg ie = 0, iedelay = 0;
+ reg ie, iedelay;
initial begin
registers[ 0] <= 0;
registers[ 9] <= 0;
registers[10] <= 0;
registers[11] <= 0;
- ie <= 0;
rd <= 1;
wr <= 0;
newcycle <= 1;
busrd <= 0;
buswr <= 0;
busaddress <= 0;
+ ie <= 0;
iedelay <= 0;
+ opcode <= 0;
+ state <= `STATE_WRITEBACK;
+ cycle <= 0;
end
always @(posedge clk)
`define EXEC_NEWCYCLE \
newcycle <= 1; rd <= 1; wr <= 0
casex (opcode)
- `INSN_LD_reg_imm8: begin
- case (cycle)
- 0: begin
- `EXEC_INC_PC;
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 1: begin
- `EXEC_INC_PC;
- if (opcode[5:3] == `INSN_reg_dHL) begin
- address <= {registers[`REG_H], registers[`REG_L]};
- wdata <= rdata;
- rd <= 0;
- wr <= 1;
- end else begin
- `EXEC_NEWCYCLE;
- end
- end
- 2: begin
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_HALT: begin
- `EXEC_NEWCYCLE;
- /* XXX Interrupts needed for HALT. */
- end
- `INSN_LD_HL_reg: begin
- case (cycle)
- 0: begin
- case (opcode[2:0])
- `INSN_reg_A: wdata <= registers[`REG_A];
- `INSN_reg_B: wdata <= registers[`REG_B];
- `INSN_reg_C: wdata <= registers[`REG_C];
- `INSN_reg_D: wdata <= registers[`REG_D];
- `INSN_reg_E: wdata <= registers[`REG_E];
- `INSN_reg_H: wdata <= registers[`REG_H];
- `INSN_reg_L: wdata <= registers[`REG_L];
- endcase
- address <= {registers[`REG_H], registers[`REG_L]};
- wr <= 1; rd <= 0;
- end
- 1: begin
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_LD_reg_HL: begin
- case(cycle)
- 0: begin
- address <= {registers[`REG_H], registers[`REG_L]};
- rd <= 1;
- end
- 1: begin
- tmp <= rdata;
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_LD_reg_reg: begin
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- case (opcode[2:0])
- `INSN_reg_A: tmp <= registers[`REG_A];
- `INSN_reg_B: tmp <= registers[`REG_B];
- `INSN_reg_C: tmp <= registers[`REG_C];
- `INSN_reg_D: tmp <= registers[`REG_D];
- `INSN_reg_E: tmp <= registers[`REG_E];
- `INSN_reg_H: tmp <= registers[`REG_H];
- `INSN_reg_L: tmp <= registers[`REG_L];
- endcase
- end
- `INSN_LD_reg_imm16: begin
- `EXEC_INC_PC;
- case (cycle)
- 0: begin
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 1: begin
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 2: begin `EXEC_NEWCYCLE; end
- endcase
- end
- `INSN_LD_SP_HL: begin
- case (cycle)
- 0: begin
- tmp <= registers[`REG_H];
- end
- 1: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- tmp <= registers[`REG_L];
- end
- endcase
- end
- `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
- case (cycle)
- 0: begin
- wr <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
- case (opcode[5:4])
- `INSN_stack_AF: wdata <= registers[`REG_A];
- `INSN_stack_BC: wdata <= registers[`REG_B];
- `INSN_stack_DE: wdata <= registers[`REG_D];
- `INSN_stack_HL: wdata <= registers[`REG_H];
- endcase
- end
- 1: begin
- wr <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
- case (opcode[5:4])
- `INSN_stack_AF: wdata <= registers[`REG_F];
- `INSN_stack_BC: wdata <= registers[`REG_C];
- `INSN_stack_DE: wdata <= registers[`REG_E];
- `INSN_stack_HL: wdata <= registers[`REG_L];
- endcase
- end
- 2: begin /* Twiddle thumbs. */ end
- 3: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
- `INSN_POP_reg: begin /* POP is 12 cycles! */
- case (cycle)
- 0: begin
- rd <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]};
- end
- 1: begin
- rd <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]};
- end
- 2: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
- `INSN_LDH_AC: begin
- case (cycle)
- 0: begin
- address <= {8'hFF,registers[`REG_C]};
- if (opcode[4]) begin // LD A,(C)
- rd <= 1;
- end else begin
- wr <= 1;
- wdata <= registers[`REG_A];
- end
- end
- 1: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
- `INSN_LDx_AHL: begin
- case (cycle)
- 0: begin
- address <= {registers[`REG_H],registers[`REG_L]};
- if (opcode[3]) begin // LDx A, (HL)
- rd <= 1;
- end else begin
- wr <= 1;
- wdata <= registers[`REG_A];
- end
- end
- 1: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
- `INSN_ALU8: begin
- if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
- // fffffffff fuck your shit, read from (HL) :(
- rd <= 1;
- address <= {registers[`REG_H], registers[`REG_L]};
- end else begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- case (opcode[2:0])
- `INSN_reg_A: tmp <= registers[`REG_A];
- `INSN_reg_B: tmp <= registers[`REG_B];
- `INSN_reg_C: tmp <= registers[`REG_C];
- `INSN_reg_D: tmp <= registers[`REG_D];
- `INSN_reg_E: tmp <= registers[`REG_E];
- `INSN_reg_H: tmp <= registers[`REG_H];
- `INSN_reg_L: tmp <= registers[`REG_L];
- `INSN_reg_dHL: tmp <= rdata;
- endcase
- end
- end
- `INSN_ALU_A: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- `INSN_NOP: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
+ `define EXECUTE
+ `include "allinsns.v"
+ `undef EXECUTE
`INSN_RST: begin
case (cycle)
0: begin
end
`STATE_WRITEBACK: begin
casex (opcode)
- `INSN_LD_reg_imm8:
- case (cycle)
- 0: begin end
- 1: case (opcode[5:3])
- `INSN_reg_A: begin registers[`REG_A] <= rdata; end
- `INSN_reg_B: begin registers[`REG_B] <= rdata; end
- `INSN_reg_C: begin registers[`REG_C] <= rdata; end
- `INSN_reg_D: begin registers[`REG_D] <= rdata; end
- `INSN_reg_E: begin registers[`REG_E] <= rdata; end
- `INSN_reg_H: begin registers[`REG_H] <= rdata; end
- `INSN_reg_L: begin registers[`REG_L] <= rdata; end
- `INSN_reg_dHL: begin /* Go off to cycle 2 */ end
- endcase
- 2: begin end
- endcase
- `INSN_HALT: begin
- /* Nothing needs happen here. */
- /* XXX Interrupts needed for HALT. */
- end
- `INSN_LD_HL_reg: begin
- /* Nothing of interest here */
- end
- `INSN_LD_reg_HL: begin
- case (cycle)
- 0: begin end
- 1: begin
- case (opcode[5:3])
- `INSN_reg_A: registers[`REG_A] <= tmp;
- `INSN_reg_B: registers[`REG_B] <= tmp;
- `INSN_reg_C: registers[`REG_C] <= tmp;
- `INSN_reg_D: registers[`REG_D] <= tmp;
- `INSN_reg_E: registers[`REG_E] <= tmp;
- `INSN_reg_H: registers[`REG_H] <= tmp;
- `INSN_reg_L: registers[`REG_L] <= tmp;
- endcase
- end
- endcase
- end
- `INSN_LD_reg_reg: begin
- case (opcode[5:3])
- `INSN_reg_A: registers[`REG_A] <= tmp;
- `INSN_reg_B: registers[`REG_B] <= tmp;
- `INSN_reg_C: registers[`REG_C] <= tmp;
- `INSN_reg_D: registers[`REG_D] <= tmp;
- `INSN_reg_E: registers[`REG_E] <= tmp;
- `INSN_reg_H: registers[`REG_H] <= tmp;
- `INSN_reg_L: registers[`REG_L] <= tmp;
- endcase
- end
- `INSN_LD_reg_imm16: begin
- case (cycle)
- 0: begin /* */ end
- 1: begin
- case (opcode[5:4])
- `INSN_reg16_BC: registers[`REG_C] <= rdata;
- `INSN_reg16_DE: registers[`REG_E] <= rdata;
- `INSN_reg16_HL: registers[`REG_L] <= rdata;
- `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
- endcase
- end
- 2: begin
- case (opcode[5:4])
- `INSN_reg16_BC: registers[`REG_B] <= rdata;
- `INSN_reg16_DE: registers[`REG_D] <= rdata;
- `INSN_reg16_HL: registers[`REG_H] <= rdata;
- `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
- endcase
- end
- endcase
- end
- `INSN_LD_SP_HL: begin
- case (cycle)
- 0: registers[`REG_SPH] <= tmp;
- 1: registers[`REG_SPL] <= tmp;
- endcase
- end
- `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
- case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- 1: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- 2: begin /* type F */ end
- 3: begin /* type F */ end
- endcase
- end
- `INSN_POP_reg: begin /* POP is 12 cycles! */
- case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
- 1: begin
- case (opcode[5:4])
- `INSN_stack_AF: registers[`REG_F] <= rdata;
- `INSN_stack_BC: registers[`REG_C] <= rdata;
- `INSN_stack_DE: registers[`REG_E] <= rdata;
- `INSN_stack_HL: registers[`REG_L] <= rdata;
- endcase
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
- end
- 2: begin
- case (opcode[5:4])
- `INSN_stack_AF: registers[`REG_A] <= rdata;
- `INSN_stack_BC: registers[`REG_B] <= rdata;
- `INSN_stack_DE: registers[`REG_D] <= rdata;
- `INSN_stack_HL: registers[`REG_H] <= rdata;
- endcase
- end
- endcase
- end
- `INSN_LDH_AC: begin
- case (cycle)
- 0: begin /* Type F */ end
- 1: if (opcode[4])
- registers[`REG_A] <= rdata;
- endcase
- end
- `INSN_LDx_AHL: begin
- case (cycle)
- 0: begin /* Type F */ end
- 1: begin
- if (opcode[3])
- registers[`REG_A] <= rdata;
- {registers[`REG_H],registers[`REG_L]} <=
- opcode[4] ? // if set, LDD, else LDI
- ({registers[`REG_H],registers[`REG_L]} - 1) :
- ({registers[`REG_H],registers[`REG_L]} + 1);
- end
- endcase
- end
- `INSN_ALU8: begin
- if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
- /* Sit on our asses. */
- end else begin /* Actually do the computation! */
- case (opcode[5:3])
- `INSN_alu_ADD: begin
- registers[`REG_A] <=
- registers[`REG_A] + tmp;
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
- /* N */ 1'b0,
- /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
- /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_ADC: begin
- registers[`REG_A] <=
- registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
- /* N */ 1'b0,
- /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
- /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_SUB: begin
- registers[`REG_A] <=
- registers[`REG_A] - tmp;
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
- /* N */ 1'b1,
- /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
- /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_SBC: begin
- registers[`REG_A] <=
- registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
- /* N */ 1'b1,
- /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
- /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_AND: begin
- registers[`REG_A] <=
- registers[`REG_A] & tmp;
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
- 3'b010,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_OR: begin
- registers[`REG_A] <=
- registers[`REG_A] | tmp;
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
- 3'b000,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_XOR: begin
- registers[`REG_A] <=
- registers[`REG_A] ^ tmp;
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
- 3'b000,
- registers[`REG_F][3:0]
- };
- end
- `INSN_alu_CP: begin
- registers[`REG_F] <=
- { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
- /* N */ 1'b1,
- /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
- /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
- registers[`REG_F][3:0]
- };
- end
- default:
- $stop;
- endcase
- end
- end
- `INSN_ALU_A: begin
- case(opcode[5:3])
- `INSN_alu_RLCA: begin
- registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
- registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
- end
- `INSN_alu_RRCA: begin
- registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
- registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
- end
- `INSN_alu_RLA: begin
- registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
- registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
- end
- `INSN_alu_RRA: begin
- registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
- registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
- end
- `INSN_alu_CPL: begin
- registers[`REG_A] <= ~registers[`REG_A];
- registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
- end
- `INSN_alu_SCF: begin
- registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
- end
- `INSN_alu_CCF: begin
- registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
- end
- endcase
- end
- `INSN_NOP: begin /* NOP! */ end
+ `define WRITEBACK
+ `include "allinsns.v"
+ `undef WRITEBACK
`INSN_RST: begin
case (cycle)
0: begin /* type F */ end
`INSN_VOP_INTR: begin
case (cycle)
0: begin end
- 1: {registers[`REG_SPH],registers[`REG_SPL]}
- <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ 1: begin end
2: begin
ie <= 0;
{registers[`REG_PCH],registers[`REG_PCL]} <=
{8'b0,jaddr};
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 2;
end
endcase
end
git.joshuawise.com / fpgaboy.git / blobdiff