It works.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa..00ee4ecee5d67c006b0adc276aac752eede763ed 100644 (file)
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;

-       wire idata = data;

        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)


@@ -46,7 +45,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
        input clk,
        input wr, rd,
        input [7:0] switches,

-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);

        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;


@@ -72,6 +71,10 @@ module CoreTop(
        
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
        
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));

+       
+       wire cclk;
+//     IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
+       assign cclk = clk;

 
        wire [15:0] addr;       
        wire [7:0] data;
 
        wire [15:0] addr;       
        wire [7:0] data;


@@ -79,7 +82,8 @@ module CoreTop(
        
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
        wire irq, tmrirq;
        wire [7:0] jaddr;

-
+       wire [1:0] state;
+       

        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),


@@ -87,7 +91,8 @@ module CoreTop(
                .buswr(wr),
                .busrd(rd),
                .irq(irq),
                .buswr(wr),
                .busrd(rd),
                .irq(irq),

-               .jaddr(jaddr));
+               .jaddr(jaddr),
+               .state(state));

        
        ROM rom(
                .address(addr),
        
        ROM rom(
                .address(addr),


@@ -97,12 +102,16 @@ module CoreTop(
                .rd(rd));
        
        AddrMon amon(
                .rd(rd));
        
        AddrMon amon(

-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .addr(addr), 
+               .clk(clk), 
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]),
+               .periods(
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );

         
        Switches sw(
                .address(addr),
         
        Switches sw(
                .address(addr),


@@ -111,24 +120,25 @@ module CoreTop(
                .wr(wr),
                .rd(rd),
                .ledout(leds),
                .wr(wr),
                .rd(rd),
                .ledout(leds),

-               .switches(switches)
+               .switches({switches[7:1],1'b0})

                );
 
        UART nouart (   /* no u */
                );
 
        UART nouart (   /* no u */

-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+               .clk(clk), 
+               .wr(wr), 
+               .rd(rd), 
+               .addr(addr), 
+               .data(data), 
+               .serial(serio)
+               );

 
 

-  InternalRAM ram(
+       InternalRAM ram(

                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),

-               .rd(rd));
+               .rd(rd)
+               );

 
        Timer tmr(
                .clk(clk),
 
        Timer tmr(
                .clk(clk),


@@ -136,7 +146,8 @@ module CoreTop(
                .rd(rd),
                .addr(addr),
                .data(data),
                .rd(rd),
                .addr(addr),
                .data(data),

-               .irq(tmrirq));
+               .irq(tmrirq)
+               );

        
        Interrupt intr(
                .clk(clk),
        
        Interrupt intr(
                .clk(clk),


@@ -162,10 +173,10 @@ module TestBench();
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
        wire irq, tmrirq;
        wire [7:0] jaddr;
        

-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire [7:0] leds;
+       wire [7:0] switches;

        
        

-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;

        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),


@@ -220,12 +231,12 @@ module TestBench();
                .master(irq),
                .jaddr(jaddr));
        
                .master(irq),
                .jaddr(jaddr));
        

-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));

 endmodule
 endmodule