Add a dirty hack to make the sim pipe directly to the readout script.

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 1f29d4aeb530c39091ab5344fed4f92465f6d2dc..7b402e4fdf7fab3d3f56a0e8e6526085320e38e8 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -145,7 +145,8 @@ module LCDC(
        reg [7:0] tileno;
        wire [10:0] tileaddr = {tileno, vypos[2:0]};
        reg [7:0] tilehigh, tilelow;
-       assign pixdata = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
+       assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);