IP

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index e0baebe3c65f9dad345554cc8137b35010ed4282..ec6223624d4b6c4325c63b46d13f5bab4c0f5cd5 100644 (file)
--- a/System.v
+++ b/System.v
@@ -1,5 +1,5 @@
-
 `timescale 1ns / 1ps
+
 module SimROM(
        input [15:0] address,
        inout [7:0] data,
@@ -137,6 +137,10 @@ module CellularRAM(
                                        progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
                                        {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
                                end
+               ADDR_PROGFLASH: if (rd || wr) begin
+                                       progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
+                                       {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
+                               end
                ADDR_MBC:       begin
                                        mbc_emul <= data;
                                        rambank <= 0;
@@ -238,6 +242,8 @@ module CoreTop(
        output wire [22:0] cr_A,
        inout [15:0] cr_DQ,
        input ps2c, ps2d,
+       output txp, txm,
+       input rxp, rxm,
 `endif
        output wire hs, vs,
        output wire [2:0] r, g,
@@ -258,10 +264,11 @@ module CoreTop(
        wire [7:0] switches = 8'b0;
        wire [3:0] buttons = 4'b0;
 `else  
-       wire xtalb, clk, vgaclk;
+       wire xtalb, clk, vgaclk, ethclk;
        IBUFG iclkbuf(.O(xtalb), .I(xtal));
-       CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+       CPUDCM cpudcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
+       ethDCM ethdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(ethclk));
        wire [7:0] ps2buttons;
 `endif
 
@@ -467,4 +474,20 @@ module CoreTop(
                .wr(wr[0]),
                .snd_data_l(soundl),
                .snd_data_r(soundr));
+
+`ifdef isim
+`else  
+       Ethernet eth(
+               .clk(clk),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .addr(addr[0]),
+               .data(data[0]),
+               .ethclk(ethclk),
+               .rxclk(xtalb),
+               .txp(txp),
+               .txm(txm),
+               .rxp(rxp),
+               .rxm(rxm));
+`endif
 endmodule