]> Joshua Wise's Git repositories - fpgaboy.git/blobdiff - rom.asm
First cut at timer
[fpgaboy.git] / rom.asm
diff --git a/rom.asm b/rom.asm
index d650855e429cdb8c222197d8c401cf8c6bb985f8..93f8524713edd8bb709ba7496a57f76d39295fcb 100644 (file)
--- a/rom.asm
+++ b/rom.asm
@@ -104,13 +104,20 @@ waitsw:
        ld hl,waitswstr
        call puts
        
+       ld c, $07
+       ld a, $07       ;start timer, 4.096KHz
+       ld [c], a
+       
        ld c, $51
        ld a, $00
        ld [c],a
        
+.loop1:
+       push bc
+       call testa
+       pop bc
        ld c, $51
        ld b, $0
-.loop1:
        ld a,[c]
        cp b
        jr z,.loop1
@@ -121,7 +128,24 @@ waitsw:
        ret
 
 waitswstr:
-       db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset.",$0D,$0A,0
+       db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
+
+testa:
+       ld c, $0F
+       ld a, [c]
+       ld b, $00
+       cp b
+       ret z
+       xor a
+       ld [c], a
+       ld hl, $D000
+       ld c, [hl]
+       inc bc
+       ld [hl], c
+       ld a, c
+       ld c, $50
+       ld [c], a
+       ret
 
 ; Core instruction basic acceptance tests.
 insntest:
@@ -167,6 +191,18 @@ insntest:
        jr .fail
        rst $00
 .jr:
+
+       ; Test inc16
+       ld d, $12
+       ld e, $FF
+       ld hl, .inc16fail
+       inc de
+       ld a, $13
+       cp d
+       jr nz, .fail
+       ld a, $00
+       cp e
+       jr nz, .fail
        
        ; Test CP.
        ld hl, .cpfail
@@ -211,6 +247,8 @@ insntest:
        db "CP",0
 .cplfail:
        db "CPL",0
+.inc16fail:
+       db "INC16",0
 .testfailed:
        db " test failed.",$0D,$0A,0
 .ok:
@@ -218,14 +256,12 @@ insntest:
 
 ; Serial port manipulation functions.
 putc:
-       push af
        ld b, 0
        ld c, $50
 .waitport:
        ld a,[c]
        cp b
        jr nz,.waitport
-       pop af
        ld [c],a
        ret
 
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