Remove gated clock and hence remove S.

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 5089129580186afd34c64690a5abfb137bded485..1f29d4aeb530c39091ab5344fed4f92465f6d2dc 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -28,10 +28,9 @@ module LCDC(
        reg clk4 = 0;
        always @(posedge clk)
                clk4 = ~clk4;
-       assign lcdclk = clk4;
        
        /***** LCD control registers *****/
-       reg [7:0] rLCDC = 8'h91;
+       reg [7:0] rLCDC = 8'h00;
        reg [7:0] rSTAT = 8'h00;
        reg [7:0] rSCY = 8'b00;
        reg [7:0] rSCX = 8'b00;
@@ -63,8 +62,8 @@ module LCDC(
        reg [8:0] posx = 9'h000;
        reg [7:0] posy = 8'h00;
        
-       wire vraminuse = (posx < 163) && (posy < 144);
-       wire oaminuse = (posx > 369) && (posy < 144);
+       wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
+       wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
        
        wire display = (posx > 2) && (posx < 163) && (posy < 144);
        
@@ -77,8 +76,9 @@ module LCDC(
        wire [7:0] vxpos = rSCX + posx - 3;
        wire [7:0] vypos = rSCY + posy;
        
-       assign lcdvs = (posy == 153) && (posx == 2);
-       assign lcdhs = (posx == 2);
+       assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
+       assign lcdhs = (posx == 2) && rLCDC[7];
+       assign lcdclk = clk4;
        
        wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
        wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;