Compiles

[fpgaboy.git] / diag.asm

diff --git a/diag.asm b/diag.asm
index c832ff2c6c6ba69de8fb24e2a3a8054a06a587b3..d269b25c1e38b186b7e9f62a700fe7fb9de181e9 100644 (file)
--- a/diag.asm
+++ b/diag.asm
@@ -33,6 +33,9 @@ main:
        ld hl, signon
        call puts
 
+       ld a, $91
+       ld [$FF40], a
+
        call putscreen
        
        ei
@@ -69,19 +72,36 @@ tiles:
        db %11111100
        db %00000000
 
+       db %01111100
+       db %11000110
+       db %11000010
+       db %11000000
+       db %11000010
+       db %11000110
+       db %01111100
+       db %00000000
+
+       db %11111100
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11111100
+       db %00000000
+
 putscreen:
+       LD A,$fc                ; $001d  Setup BG palette
+       LD [$FF47],A    ; $001f
+
        ; Wait for vblank
        call .vblwait
 
        ld hl, $8000    ; Copy two tiles.
        ld de, tiles
-       ld c, $10
-.cloop:        push hl
-       ld h, d
-       ld l, e
-       ld a, [hl]
+       ld c, $20
+.cloop:        ld a, [de]
        inc de
-       pop hl
        ld [hli], a
        ld [hli], a
        dec c
@@ -93,9 +113,9 @@ putscreen:
 .vloop:        call .vblwait
        ld c, $40
        ld b, 0
-.loop: inc b
-       ld a, b
-       and $01
+.loop: ld a, b
+       inc b
+       and $03
        ld [hli], a
        ld a, h
        cp $9C
@@ -127,30 +147,19 @@ vbl:
        ld [$FF0F], a
 
        ld a, [$FF51]
-       ld b, a
-       and $80
-       cp $80
-       jr nz, .nothing
-       ld c, $0
+       bit 7, a
+       jr z, .nothing
 
-       ld a, b
-       and $1
-       cp c
+       bit 0, a
        call nz, .scyup
        
-       ld a, b
-       and $2
-       cp c
+       bit 1, a
        call nz, .scydown
        
-       ld a, b
-       and $4
-       cp c
+       bit 2, a
        call nz, .scxup
        
-       ld a, b
-       and $8
-       cp c
+       bit 3, a
        call nz, .scxdown
 
 .nothing:
@@ -312,8 +321,8 @@ waitsw:
        ld a,[c]
        cp $0
        jr z,.loop1
-.loop2:
-       ld a,[c]
+
+.loop2:        ld a,[c]
        cp $0
        jr nz,.loop2
        ret