Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 0afc09066159f17645bd92537eab33fc43f5f908..5b0fb3cc45f05c81f58e96f7263b386e4eaf1619 100644 (file)
--- a/System.v
+++ b/System.v
@@ -71,14 +71,15 @@ module CoreTop(
        
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
+       
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        
        wire irq, tmrirq;
        wire [7:0] jaddr;
-
+       wire [1:0] state;
+       
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
@@ -86,7 +87,8 @@ module CoreTop(
                .buswr(wr),
                .busrd(rd),
                .irq(irq),
-               .jaddr(jaddr));
+               .jaddr(jaddr),
+               .state(state));
        
        ROM rom(
                .address(addr),
@@ -100,7 +102,12 @@ module CoreTop(
                .clk(clk), 
                .digit(digits), 
                .out(seven),
-               .freeze(buttons[0]));
+               .freeze(buttons[0]),
+               .periods(
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
                .address(addr),
@@ -165,7 +172,7 @@ module TestBench();
        wire [7:0] leds;
        wire [7:0] switches;
        
-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),