Some LCDC IRQ stuffs. Working on fixing ldm_a

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 0afc09066159f17645bd92537eab33fc43f5f908..2bb0613f8d725402c459b097a462a75ee6cca45c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -67,18 +67,22 @@ module CoreTop(
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
-       output wire [7:0] seven);
+       output wire [7:0] seven,
+       output wire hs, vs,
+       output wire [2:0] r, g,
+       output wire [1:0] b);
        
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
+       
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        
-       wire irq, tmrirq;
+       wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;
-
+       wire [1:0] state;
+       
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
@@ -86,7 +90,8 @@ module CoreTop(
                .buswr(wr),
                .busrd(rd),
                .irq(irq),
-               .jaddr(jaddr));
+               .jaddr(jaddr),
+               .state(state));
        
        ROM rom(
                .address(addr),
@@ -95,12 +100,31 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
        
+       LCDC lcdc(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .lcdcirq(lcdcirq),
+               .vblankirq(vblankirq),
+               .vgahs(hs),
+               .vgavs(vs),
+               .vgar(r),
+               .vgag(g),
+               .vgab(b));
+       
        AddrMon amon(
                .addr(addr), 
                .clk(clk), 
                .digit(digits), 
                .out(seven),
-               .freeze(buttons[0]));
+               .freeze(buttons[0]),
+               .periods(
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
                .address(addr),
@@ -144,8 +168,8 @@ module CoreTop(
                .wr(wr),
                .addr(addr),
                .data(data),
-               .vblank(0),
-               .lcdc(0),
+               .vblank(vblankirq),
+               .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(0),
                .buttons(0),
@@ -165,7 +189,7 @@ module TestBench();
        wire [7:0] leds;
        wire [7:0] switches;
        
-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),