Fix ADD HL,xx.

[fpgaboy.git] / core / insn_add_hl.v

diff --git a/core/insn_add_hl.v b/core/insn_add_hl.v
index 0d85f953f5713ec704c696b927a4018094d96a55..6bd7e7a8dc17e8599cf6497eeb46b835cca827fd 100644 (file)
--- a/core/insn_add_hl.v
+++ b/core/insn_add_hl.v
@@ -20,15 +20,14 @@
 `ifdef WRITEBACK
        `INSN_ADD_HL: begin
                case (cycle)
-               0:      {tmp,tmp2} <= `_HL + {tmp,tmp2};
                1:      begin
                                `_F <=  { /* Z */ `_F[7],
                                          /* N */ 1'b0,
                                          /* H */ (({`_HL} + {tmp,tmp2}) & 16'h1000) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) >> 16 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) & 17'h10000) ? 1'b1 : 1'b0,
                                          `_F[3:0]
                                        };
-                               `_HL <= {tmp, tmp2};
+                               `_HL <= `_HL + {tmp, tmp2};
                        end
                endcase
        end