Ethernet TX support

[fpgaboy.git] / core / insn_incdec_reg8.v

diff --git a/core/insn_incdec_reg8.v b/core/insn_incdec_reg8.v
index e89ceba54d63903c91776137d37ba5df4b78e729..b7ed993068cd38cee0a5e87b09c4f99366a9eb30 100644 (file)
--- a/core/insn_incdec_reg8.v
+++ b/core/insn_incdec_reg8.v
@@ -5,13 +5,13 @@
                `EXEC_INC_PC
                `EXEC_NEWCYCLE
                case (opcode[5:3])
                `EXEC_INC_PC
                `EXEC_NEWCYCLE
                case (opcode[5:3])

-               `INSN_reg_A:    tmp <= `_A;
-               `INSN_reg_B:    tmp <= `_B;
-               `INSN_reg_C:    tmp <= `_C;
-               `INSN_reg_D:    tmp <= `_D;
-               `INSN_reg_E:    tmp <= `_E;
-               `INSN_reg_H:    tmp <= `_H;
-               `INSN_reg_L:    tmp <= `_L;
+               `INSN_reg_A:    tmp <= `_A + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_B:    tmp <= `_B + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_C:    tmp <= `_C + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_D:    tmp <= `_D + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_E:    tmp <= `_E + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_H:    tmp <= `_H + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_L:    tmp <= `_L + (opcode[0] ? 8'hFF : 8'h01);

                endcase
        end
 `endif
                endcase
        end
 `endif


@@ -19,18 +19,19 @@
 `ifdef WRITEBACK
        `INSN_INCDEC_reg8: begin
                case (opcode[5:3])
 `ifdef WRITEBACK
        `INSN_INCDEC_reg8: begin
                case (opcode[5:3])

-               `INSN_reg_A:    `_A <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_B:    `_B <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_C:    `_C <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_D:    `_D <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_E:    `_E <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_H:    `_H <= tmp + (opcode[0] ? 8'hFF : 8'h01);
-               `INSN_reg_L:    `_L <= tmp + (opcode[0] ? 8'hFF : 8'h01);
+               `INSN_reg_A:    `_A <= tmp;
+               `INSN_reg_B:    `_B <= tmp;
+               `INSN_reg_C:    `_C <= tmp;
+               `INSN_reg_D:    `_D <= tmp;
+               `INSN_reg_E:    `_E <= tmp;
+               `INSN_reg_H:    `_H <= tmp;
+               `INSN_reg_L:    `_L <= tmp;

                endcase
                `_F <= {
                endcase
                `_F <= {

-                               ((tmp + (opcode[0] ? 8'hFF : 8'h01)) == 8'h00) ? 1'b1 : 1'b0,
-                               1'b0,
-                               (({1'b0,tmp[3:0]} + (opcode[0] ? 5'h1F : 5'h01)) >> 4) ? 1'b1 : 1'b0,
-                               `_F[4:0]};
+                               (tmp == 8'h00) ? 1'b1 : 1'b0,   /* Z */
+                               opcode[0],       /* N */
+                               (tmp[3:0] == (opcode[0] ? 4'hF : 4'h0)) ? 1'b1 : 1'b0,
+                               `_F[4:0]
+                       };

        end
 `endif
        end
 `endif