Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY...

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index 1f0ae7d0d31c57fbc648a6aab693e9fbd77fc367..07f996a6a475add8a984a934271bba2c36f25b56 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -10,11 +10,12 @@ module UART(
        input [15:0] addr,
        inout [7:0] data,
        output reg serial = 1);
-       
+
+       reg rdlatch = 0;
        wire decode = (addr == `MMAP_ADDR);
        
        wire [7:0] odata;
-       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       assign data = rdlatch ? odata : 8'bzzzzzzzz;
 
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
@@ -25,8 +26,9 @@ module UART(
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
-       always @ (negedge clk)
+       always @ (posedge clk)
        begin
+               rdlatch <= rd && decode;
                /* deal with diqing */
                if(newdata) begin
                        data_stor <= data;