Yaaay, everything is posedge now

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1182b327709e7d4cd3fc24e52fd2a128cd46d1c1..9db958fa85dc93189a0251b91d1b8cb5c600ff97 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -146,9 +146,12 @@
 
 module GBZ80Core(
        input clk,
-       output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
-       inout [7:0] busdata,
-       output reg buswr, output reg busrd,
+       inout [15:0] bus0address,       /* BUS_* is latched on STATE_FETCH. */
+       inout [7:0] bus0data,
+       inout bus0wr, bus0rd,
+       inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
+       inout [7:0] bus1data,
+       inout bus1wr, bus1rd,
        input irq, input [7:0] jaddr,
        output reg [1:0] state);
 
@@ -167,7 +170,24 @@ module GBZ80Core(
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
-       assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
+       wire [7:0] busdata;
+       
+       reg [15:0] busaddress;
+       reg buswr, busrd;
+       
+       reg bootstrap_enb;
+       
+       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF));  /* 0 or 1 depending on which bus */
+               
+       assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
+       assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
+       assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
+       assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
+       assign busdata = (bus == 0) ? bus0data : bus1data;
+       assign bus0rd = (bus == 0) ? busrd : 1'bz;
+       assign bus1rd = (bus == 1) ? busrd : 1'bz;
+       assign bus0wr = (bus == 0) ? buswr : 1'bz;
+       assign bus1wr = (bus == 1) ? buswr : 1'bz;
 
        reg ie, iedelay;
 
@@ -257,9 +277,10 @@ module GBZ80Core(
                state <= `STATE_WRITEBACK;
                cycle <= 0;
                twobyte <= 0;
+               bootstrap_enb <= 1;
        end
 
-       always @(posedge clk)
+       always @(negedge clk)   /* Set things up at the negedge to prepare for the posedge. */
                case (state)
                `STATE_FETCH: begin
                        if (newcycle) begin
@@ -273,6 +294,15 @@ module GBZ80Core(
                                if (wr)
                                        buswdata <= wdata;
                        end
+               end
+               `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
+               end
+               endcase
+       
+       always @(posedge clk)
+               case (state)
+               `STATE_FETCH: begin
+                       /* Things are set up in negedge so that something looking on posedge will get his shit. */
                        state <= `STATE_DECODE;
                end
                `STATE_DECODE: begin
@@ -284,8 +314,8 @@ module GBZ80Core(
                                        opcode <= `INSN_VOP_INTR;
                                else
                                        opcode <= {1'b0,busdata};
-                               rdata <= busdata;
                                newcycle <= 0;
+                               rdata <= busdata;
                                cycle <= 0;
                        end else begin
                                if (rd) rdata <= busdata;
@@ -295,10 +325,10 @@ module GBZ80Core(
                                ie <= 1;
                                iedelay <= 0;
                        end
-                       buswr <= 0;
-                       busrd <= 0;
                        wr <= 0;
                        rd <= 0;
+                       buswr <= 0;
+                       busrd <= 0;
                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;