`define INSN_BIT 9'b101xxxxxx
`define INSN_RES 9'b110xxxxxx
`define INSN_SET 9'b111xxxxxx
+`define INSN_ADD_HL 9'b000xx1001
`define INSN_cc_NZ 2'b00
`define INSN_cc_Z 2'b01
inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */
inout [7:0] bus1data,
inout bus1wr, bus1rd,
- input irq, input [7:0] jaddr,
+ input irq, output reg irqack, input [7:0] jaddr,
output reg [1:0] state);
// reg [1:0] state; /* State within this bus cycle (see STATE_*). */
cycle <= 0;
twobyte <= 0;
bootstrap_enb <= 1;
+ irqack <= 0;
end
always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */
busaddress <= address;
buswr <= wr;
busrd <= rd;
- if (wr)
+ if (wr) begin
buswdata <= wdata;
+ if (address == 16'hFF50)
+ bootstrap_enb <= 0;
+ end
end
end
`STATE_DECODE: begin /* Make sure this only happens for one clock. */
end
wr <= 0;
rd <= 0;
- buswr <= 0;
- busrd <= 0;
address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
wdata <= 8'bxxxxxxxx;
state <= `STATE_EXECUTE;
end
`STATE_EXECUTE: begin
+ `ifdef isim
if (opcode[7:0] === 8'bxxxxxxxx)
$stop;
+ `endif
casex (opcode)
`define EXECUTE
`include "allinsns.v"