Make binwire a little bit more error-resistant

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 8970e5d7132861495e894b319f8f3510f85333e2..3c2f7702aaa1c9e507232c435029c0a4456f48cf 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -295,8 +295,11 @@ module GBZ80Core(
                                busaddress <= address;
                                buswr <= wr;
                                busrd <= rd;
-                               if (wr)
+                               if (wr) begin
                                        buswdata <= wdata;
+                                       if (address == 16'hFF50)
+                                               bootstrap_enb <= 0;
+                               end
                        end
                end
                `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
@@ -333,8 +336,6 @@ module GBZ80Core(
                        end
                        wr <= 0;
                        rd <= 0;
-                       buswr <= 0;
-                       busrd <= 0;
                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;