Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY...

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 95b715cd322e0806612ad899662648027a675c7a..b1d4c3d90241b3aaab8ac4f103e1dbf292c177b9 100644 (file)
--- a/System.v
+++ b/System.v
@@ -262,11 +262,11 @@ module CoreTop(
                .data(data[0]),
                .clk(clk),
                .wr(wr[0]),
-               .rd(rd[0])
+               .rd(rd[0]),
                .cr_nADV(cr_nADV),
                .cr_nCE(cr_nCE),
                .cr_nOE(cr_nOE),
-               .cr_nWR(cr_nWE),
+               .cr_nWE(cr_nWE),
                .cr_CRE(cr_CRE),
                .cr_nLB(cr_nLB),
                .cr_nUB(cr_nUB),