INC -> INCDEC

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e0857397709655af2e502193b040a6db051c117c..33e7be6a12e18a4cafe5fdf9013fc4bd2f1e2b35 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -11,6 +11,25 @@
 `define REG_PCH        10
 `define REG_PCL        11
 
+`define _A     registers[`REG_A]
+`define _B     registers[`REG_B]
+`define _C     registers[`REG_C]
+`define _D     registers[`REG_D]
+`define _E     registers[`REG_E]
+`define _F     registers[`REG_F]
+`define _H     registers[`REG_H]
+`define _L     registers[`REG_L]
+`define _SPH   registers[`REG_SPH]
+`define _SPL   registers[`REG_SPL]
+`define _PCH   registers[`REG_PCH]
+`define _PCL   registers[`REG_PCL]
+`define _AF    {`_A, `_F}
+`define _BC    {`_B, `_C}
+`define _DE    {`_D, `_E}
+`define _HL    {`_H, `_L}
+`define _SP    {`_SPH, `_SPL}
+`define _PC    {`_PCH, `_PCL}
+
 `define FLAG_Z 8'b10000000
 `define FLAG_N 8'b01000000
 `define FLAG_H 8'b00100000
@@ -33,6 +52,7 @@
 `define INSN_LDH_AC            8'b111x0010     // Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL           8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8              8'b10xxxxxx     // 10 xxx yyy
+`define INSN_ALU8IMM           8'b11xxx110
 `define INSN_NOP               8'b00000000
 `define INSN_RST               8'b11xxx111
 `define INSN_RET               8'b110x1001     // 1 = RETI, 0 = RET
@@ -49,6 +69,8 @@
 `define INSN_VOP_INTR          8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
 `define INSN_DI                        8'b11110011
 `define INSN_EI                        8'b11111011
+`define INSN_INCDEC_HL         8'b0011010x
+`define INSN_INCDEC_reg8       8'b00xxx10x
 
 `define INSN_cc_NZ             2'b00
 `define INSN_cc_Z              2'b01
@@ -88,14 +110,21 @@
 `define INSN_alu_SCF           3'b110
 `define INSN_alu_CCF           3'b111
 
+`define EXEC_INC_PC            `_PC <= `_PC + 1;
+`define EXEC_NEXTADDR_PCINC    address <= `_PC + 1;
+`define EXEC_NEWCYCLE          begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da)     begin address <= (ad); wdata <= (da); wr <= 1; end end
+`define EXEC_READ(ad)          begin address <= (ad); rd <= 1; end end
+
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
        output reg buswr, output reg busrd,
-       input irq, input [7:0] jaddr);
+       input irq, input [7:0] jaddr,
+       output reg [1:0] state);
        
-       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+//     reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
        reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];
@@ -184,24 +213,10 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
-`define EXEC_INC_PC \
-       {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-       address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-       newcycle <= 1; rd <= 1; wr <= 0
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
                        `undef EXECUTE
-                       `INSN_DI: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end
-                       `INSN_EI: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end
                        default:
                                $stop;
                        endcase