Modify the diagrom to test two byte insns

[fpgaboy.git] / insn_ret-retcc.v

diff --git a/insn_ret-retcc.v b/insn_ret-retcc.v
index ef890039d3ce8f45bf9d9ab6c0edc336807a3692..bad4c04d9f457df84e67b0d230cbd4d7d1008129 100644 (file)
--- a/insn_ret-retcc.v
+++ b/insn_ret-retcc.v
@@ -1,30 +1,20 @@
 `ifdef EXECUTE
        `INSN_RET,`INSN_RETCC: begin
                case (cycle)
 `ifdef EXECUTE
        `INSN_RET,`INSN_RETCC: begin
                case (cycle)

-               0:      begin
-                               rd <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                       end
+               0:      `EXEC_READ(`_SP)

                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
                1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!

-                               `EXEC_INC_PC;   // cycle 1 is skipped if we are not retcc
+                               `EXEC_INC_PC    // cycle 1 is skipped if we are not retcc

                                case (opcode[4:3])
                                case (opcode[4:3])

-                               `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                               `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                               `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                               `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                               `INSN_cc_NZ:    if (registers[`REG_F][7]) `EXEC_NEWCYCLE
+                               `INSN_cc_Z:     if (~registers[`REG_F][7]) `EXEC_NEWCYCLE
+                               `INSN_cc_NC:    if (registers[`REG_F][4]) `EXEC_NEWCYCLE
+                               `INSN_cc_C:     if (~registers[`REG_F][4]) `EXEC_NEWCYCLE

                                endcase
                                endcase

-                               rd <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                       end
-               2:      begin
-                               rd <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                               `EXEC_READ(`_SP)        // retry the read

                        end
                        end

+               2:      `EXEC_READ(`_SP + 1)

                3:      begin /* twiddle thumbs */ end
                3:      begin /* twiddle thumbs */ end

-               4:      begin
-                               `EXEC_NEWCYCLE;
-                               // do NOT increment PC!
-                       end
+               4:      `EXEC_NEWCYCLE

                endcase
        end
 `endif
                endcase
        end
 `endif


@@ -35,11 +25,10 @@
                0:      if (opcode[0])  // i.e., not RETCC
                                cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
                1:      begin /* Nothing need happen here. */ end
                0:      if (opcode[0])  // i.e., not RETCC
                                cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
                1:      begin /* Nothing need happen here. */ end

-               2:      registers[`REG_PCL] <= rdata;
-               3:      registers[`REG_PCH] <= rdata;
+               2:      `_PCL <= rdata;
+               3:      `_PCH <= rdata;

                4:      begin
                4:      begin

-                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+                               `_SP <= `_SP + 2;

                                if (opcode[4] && opcode[0])     /* RETI */
                                        ie <= 1;
                        end
                                if (opcode[4] && opcode[0])     /* RETI */
                                        ie <= 1;
                        end