Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY...
[fpgaboy.git] / insn_jr-jrcc.v
index 7a869b3..767db6a 100644 (file)
@@ -2,25 +2,22 @@
        `INSN_JR_imm,`INSN_JRCC_imm: begin
                case (cycle)
                0:      begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEXTADDR_PCINC;
-                               rd <= 1;
+                               `EXEC_INC_PC
+                               `EXEC_READ(`_PC + 1)
                        end
-               1: begin
-                               `EXEC_INC_PC;
+               1:      begin
+                               `EXEC_INC_PC
                                if (opcode[5]) begin    // i.e., JP cc,nn
                                        /* We need to check the condition code to bail out. */
                                        case (opcode[4:3])
-                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                       `INSN_cc_NZ:    if (`_F[7]) `EXEC_NEWCYCLE
+                                       `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
+                                       `INSN_cc_NC:    if (`_F[4]) `EXEC_NEWCYCLE
+                                       `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE
                                        endcase
                                end
                        end
-               2:      begin
-                               `EXEC_NEWCYCLE;
-                       end
+               2:      `EXEC_NEWCYCLE
                endcase
        end
 `endif
@@ -30,9 +27,7 @@
                case (cycle)
                0:      begin /* type F */ end
                1:      tmp <= rdata;
-               2:      {registers[`REG_PCH],registers[`REG_PCL]} <=
-                               {registers[`REG_PCH],registers[`REG_PCL]} +
-                               {tmp[7]?8'hFF:8'h00,tmp};
+               2:      `_PC <= `_PC + {tmp[7]?8'hFF:8'h00,tmp};
                endcase
        end
 `endif
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