Semi-working, but prone to anus, keyboard driver

[fpgaboy.git] / insn_rst.v

diff --git a/insn_rst.v b/insn_rst.v
index 8752034dd4f2c8f48742f3598469f976f0a46bfc..4b65032179092d8753d834e11e8aac232e706a4c 100644 (file)
--- a/insn_rst.v
+++ b/insn_rst.v
@@ -1,23 +1,12 @@
 `ifdef EXECUTE
        `INSN_RST: begin
                case (cycle)
 `ifdef EXECUTE
        `INSN_RST: begin
                case (cycle)

-               0:      begin
-                               `EXEC_INC_PC;           // This goes FIRST in RST
-                       end
-               1:      begin
-                               wr <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-                               wdata <= registers[`REG_PCH];
-                       end
-               2:      begin
-                               wr <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
-                               wdata <= registers[`REG_PCL];
-                       end
+               0:      `EXEC_INC_PC            // This goes FIRST in RST
+               1:      `EXEC_WRITE(`_SP - 1, `_PCH)
+               2:      `EXEC_WRITE(`_SP - 2, `_PCL)

                3:      begin
                3:      begin

-                               `EXEC_NEWCYCLE;
-                               {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                       {10'b0,opcode[5:3],3'b0};
+                               `EXEC_NEWCYCLE
+                               `_PC <= {10'b0,opcode[5:3],3'b0};

                        end
                endcase
        end
                        end
                endcase
        end


@@ -29,8 +18,7 @@
                0:      begin /* type F */ end
                1:      begin /* type F */ end
                2:      begin /* type F */ end
                0:      begin /* type F */ end
                1:      begin /* type F */ end
                2:      begin /* type F */ end

-               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                               {registers[`REG_SPH],registers[`REG_SPL]}-2;
+               3:      `_SP <= `_SP - 2;

                endcase
        end
 `endif
                endcase
        end
 `endif