`INSN_CALL,`INSN_CALLCC: begin
case (cycle)
0: begin
- `EXEC_INC_PC;
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
+ `EXEC_INC_PC
+ `EXEC_READ(`_PC + 1)
end
1: begin
- `EXEC_INC_PC;
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
+ `EXEC_INC_PC
+ `EXEC_READ(`_PC + 1)
end
2: begin
- `EXEC_INC_PC;
+ `EXEC_INC_PC
if (!opcode[0]) // i.e., is callcc
/* We need to check the condition code to bail out. */
case (opcode[4:3])
- `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
- `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
- `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
- `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE
+ `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE
+ `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE
+ `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE
endcase
end
- 3: begin
- address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- wdata <= registers[`REG_PCH];
- wr <= 1;
- end
- 4: begin
- address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
- wdata <= registers[`REG_PCL];
- wr <= 1;
- end
- 5: begin
- `EXEC_NEWCYCLE; /* do NOT increment the PC */
- end
+ 3: `EXEC_WRITE(`_SP - 1, `_PCH)
+ 4: `EXEC_WRITE(`_SP - 2, `_PCL)
+ 5: `EXEC_NEWCYCLE
endcase
end
`endif
1: tmp <= rdata; // tmp contains newpcl
2: tmp2 <= rdata; // tmp2 contains newpch
3: begin /* type F */ end
- 4: registers[`REG_PCH] <= tmp2;
- 5: begin
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 2;
- registers[`REG_PCL] <= tmp;
+ 4: `_PCH <= tmp2;
+ 5: begin
+ `_PCL <= tmp;
+ `_SP <= `_SP - 2;
end
endcase
end