First cut at timer

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 8bc14e9df01a67155742346789f38a6f3bacb76c..a5fee66e243e92a9079e66331d929075fe2e120d 100644 (file)
--- a/System.v
+++ b/System.v
@@ -70,9 +70,7 @@ module CoreTop(
        output wire [3:0] digits,
        output wire [7:0] seven);
        
        output wire [3:0] digits,
        output wire [7:0] seven);
        

-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
-       
+       wire clk;       

        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
        wire [15:0] addr;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
 
        wire [15:0] addr;       


@@ -111,7 +109,7 @@ module CoreTop(
                .switches(switches)
                );
 
                .switches(switches)
                );
 

-       UART nouart (
+       UART nouart (   /* no u */

     .clk(clk), 
     .wr(wr), 
     .rd(rd), 
     .clk(clk), 
     .wr(wr), 
     .rd(rd), 


@@ -126,6 +124,30 @@ module CoreTop(
                .clk(clk),
                .wr(wr),
                .rd(rd));
                .clk(clk),
                .wr(wr),
                .rd(rd));

+
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));

 endmodule
 
 module TestBench();
 endmodule
 
 module TestBench();


@@ -168,6 +190,30 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
                .rd(rd),
                .serial(serio));
        

+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
+       

 //     Switches sw(
 //             .clk(clk),
 //             .address(addr),
 //     Switches sw(
 //             .clk(clk),
 //             .address(addr),