Merge andrew:/afs/andrew/usr/czl/public/FPGABoy

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 62f976be7dc3d4f8062de7ad4c07d88131d435a4..931e90029c7c2c438fed2c2a7c6726baf7e4c008 100644 (file)
--- a/System.v
+++ b/System.v
@@ -262,7 +262,7 @@ module CoreTop(
        wire [7:0] data [1:0];
        wire wr [1:0], rd [1:0];
        
-       wire irq, tmrirq, lcdcirq, vblankirq;
+       wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
        wire [7:0] jaddr;
        wire [1:0] state;
        wire ack;
@@ -357,6 +357,16 @@ module CoreTop(
                .ledout(leds),
                .switches(switches)
                );
+       
+       Buttons ass(
+               .core_clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .int(btnirq),
+               .buttons(switches)
+               );
 
        AddrMon amon(
                .clk(clk), 
@@ -415,7 +425,7 @@ module CoreTop(
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(1'b0),
-               .buttons(1'b0),
+               .buttons(btnirq),
                .master(irq),
                .ack(ack),
                .jaddr(jaddr));