Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index dec02b8bfadc766aa96bc76aa6130be9ca82936c..5b0fb3cc45f05c81f58e96f7263b386e4eaf1619 100644 (file)
--- a/System.v
+++ b/System.v
@@ -22,20 +22,19 @@ module InternalRAM(
        input wr, rd);
        
        // synthesis attribute ram_style of reg is block
-       reg [7:0] ram [2047:0];
+       reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
-       wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
-               if (decode)
-               begin
-                       if (wr)
-                               ram[address[10:0]] <= data;
-                       odata <= ram[address[10:0]];
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[12:0]] <= data;
+                       odata <= ram[address[12:0]];
                end
        end
 endmodule
@@ -46,7 +45,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
@@ -70,21 +69,26 @@ module CoreTop(
        output wire [3:0] digits,
        output wire [7:0] seven);
        
-       wire clk;
-       //IBUFG ibuf (.O(clk), .I(iclk));
-       
+       wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
-
+       
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
-
+       
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       wire [1:0] state;
+       
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr),
+               .state(state));
        
        ROM rom(
                .address(addr),
@@ -94,12 +98,16 @@ module CoreTop(
                .rd(rd));
        
        AddrMon amon(
-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .addr(addr), 
+               .clk(clk), 
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]),
+               .periods(
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
                .address(addr),
@@ -111,39 +119,68 @@ module CoreTop(
                .switches(switches)
                );
 
-       UART nouart (
-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+       UART nouart (   /* no u */
+               .clk(clk), 
+               .wr(wr), 
+               .rd(rd), 
+               .addr(addr), 
+               .data(data), 
+               .serial(serio)
+               );
 
-  InternalRAM ram(
+       InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
-               .rd(rd));
+               .rd(rd)
+               );
+
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq)
+               );
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
 endmodule
 
 module TestBench();
-       reg clk = 0;
+       reg clk = 1;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        
-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       
+       wire [7:0] leds;
+       wire [7:0] switches;
        
-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .clk(clk),
@@ -168,12 +205,34 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Timer tmr(
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .irq(tmrirq));
+       
+       Interrupt intr(
+               .clk(clk),
+               .rd(rd),
+               .wr(wr),
+               .addr(addr),
+               .data(data),
+               .vblank(0),
+               .lcdc(0),
+               .tovf(tmrirq),
+               .serial(0),
+               .buttons(0),
+               .master(irq),
+               .jaddr(jaddr));
+       
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));
 endmodule