RETCC that breaks everything. Why?

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index dec02b8bfadc766aa96bc76aa6130be9ca82936c..8bc14e9df01a67155742346789f38a6f3bacb76c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -22,7 +22,7 @@ module InternalRAM(
        input wr, rd);
        
        // synthesis attribute ram_style of reg is block
-       reg [7:0] ram [2047:0];
+       reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
@@ -31,11 +31,11 @@ module InternalRAM(
        
        always @(negedge clk)
        begin
-               if (decode)
-               begin
-                       if (wr)
-                               ram[address[10:0]] <= data;
-                       odata <= ram[address[10:0]];
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[12:0]] <= data;
+                       odata <= ram[address[12:0]];
                end
        end
 endmodule