LD with HLs

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e5a7d35e16262ccfa113e892f147e39f9260adee..738bf917a1b0a4c4ab202726e6002834127ac2ff 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -130,13 +130,42 @@ module GBZ80Core(
                                endcase
                        end
                        `INSN_HALT: begin
-                               /* XXX UNIMP */
+                               `EXEC_NEWCYCLE;
+                               /* XXX Interrupts needed for HALT. */
                        end
                        `INSN_LD_HL_reg: begin
-                               /* XXX UNIMP */
+                               case (cycle)
+                               0:      begin
+                                               case (opcode[2:0])
+                                               `INSN_reg_A:    begin wdata <= registers[`REG_A]; end
+                                               `INSN_reg_B:    begin wdata <= registers[`REG_B]; end
+                                               `INSN_reg_C:    begin wdata <= registers[`REG_C]; end
+                                               `INSN_reg_D:    begin wdata <= registers[`REG_D]; end
+                                               `INSN_reg_E:    begin wdata <= registers[`REG_E]; end
+                                               `INSN_reg_H:    begin wdata <= registers[`REG_H]; end
+                                               `INSN_reg_L:    begin wdata <= registers[`REG_L]; end
+                                               endcase
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 1; rd <= 0;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
                        end
                        `INSN_LD_reg_HL: begin
-                               /* XXX UNIMP */
+                               case(cycle)
+                               0: begin
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 0; rd <= 1;
+                                       end
+                               1: begin
+                                               tmp <= rdata;
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
                        end
                        `INSN_LD_reg_reg: begin
                                `EXEC_INC_PC;
@@ -172,13 +201,31 @@ module GBZ80Core(
                                        2: cycle <= 0;
                                        endcase
                                `INSN_HALT: begin
-                                       /* XXX UNIMP */
+                                       /* Nothing needs happen here. */
+                                       /* XXX Interrupts needed for HALT. */
                                end
                                `INSN_LD_HL_reg: begin
-                                       /* XXX UNIMP */
+                                       case (cycle)
+                                       0: cycle <= 1;
+                                       1: cycle <= 0;
+                                       endcase
                                end
                                `INSN_LD_reg_HL: begin
-                                       /* XXX UNIMP */
+                                       case (cycle)
+                                       0:      cycle <= 1;
+                                       1:      begin
+                                                       case (opcode[5:3])
+                                                       `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
+                                                       `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
+                                                       `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
+                                                       `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
+                                                       `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
+                                                       `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
+                                                       `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                                       endcase
+                                                       cycle <= 0;
+                                               end
+                                       endcase
                                end
                                `INSN_LD_reg_reg: begin
                                        case (opcode[5:3])