Fix RAM bugs with kludge. Fix CALL bug. CALL test case.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e5a7d35e16262ccfa113e892f147e39f9260adee..ec1756ebe3b6ed66c171327c5b8caa67990325e8 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -26,6 +26,18 @@
 `define INSN_LD_HL_reg         8'b01110xxx
 `define INSN_LD_reg_HL         8'b01xxx110
 `define INSN_LD_reg_reg                8'b01xxxxxx
 `define INSN_LD_HL_reg         8'b01110xxx
 `define INSN_LD_reg_HL         8'b01xxx110
 `define INSN_LD_reg_reg                8'b01xxxxxx

+`define INSN_LD_reg_imm16      8'b00xx0001
+`define INSN_LD_SP_HL          8'b11111001
+`define INSN_PUSH_reg          8'b11xx0101
+`define INSN_POP_reg                   8'b11xx0001
+`define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A
+`define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
+`define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
+`define INSN_NOP                               8'b00000000
+`define INSN_RST                               8'b11xxx111
+`define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
+`define INSN_CALL                              8'b11001101
+

 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 `define INSN_reg_C             3'b001
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 `define INSN_reg_C             3'b001


@@ -34,6 +46,22 @@
 `define INSN_reg_H             3'b100
 `define INSN_reg_L             3'b101
 `define INSN_reg_dHL   3'b110
 `define INSN_reg_H             3'b100
 `define INSN_reg_L             3'b101
 `define INSN_reg_dHL   3'b110

+`define INSN_reg16_BC  2'b00
+`define INSN_reg16_DE  2'b01
+`define INSN_reg16_HL  2'b10
+`define INSN_reg16_SP  2'b11
+`define INSN_stack_AF  2'b11
+`define INSN_stack_BC  2'b00
+`define INSN_stack_DE  2'b01
+`define INSN_stack_HL  2'b10
+`define INSN_alu_ADD           3'b000
+`define INSN_alu_ADC           3'b001
+`define INSN_alu_SUB           3'b010
+`define INSN_alu_SBC           3'b011
+`define INSN_alu_AND           3'b100
+`define INSN_alu_XOR           3'b101
+`define INSN_alu_OR            3'b110
+`define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?

 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,


@@ -53,24 +81,26 @@ module GBZ80Core(
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg rd = 1, wr = 0, newcycle = 1;
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg rd = 1, wr = 0, newcycle = 1;
        

-       reg [7:0] tmp;                                  /* Generic temporary reg. */
+       reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */

        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        

+       reg ie = 0;
+       

        initial begin
        initial begin

-               registers[ 0] = 0;
-               registers[ 1] = 0;
-               registers[ 2] = 0;
-               registers[ 3] = 0;
-               registers[ 4] = 0;
-               registers[ 5] = 0;
-               registers[ 6] = 0;
-               registers[ 7] = 0;
-               registers[ 8] = 0;
-               registers[ 9] = 0;
-               registers[10] = 0;
-               registers[11] = 0;
+               registers[ 0] <= 0;
+               registers[ 1] <= 0;
+               registers[ 2] <= 0;
+               registers[ 3] <= 0;
+               registers[ 4] <= 0;
+               registers[ 5] <= 0;
+               registers[ 6] <= 0;
+               registers[ 7] <= 0;
+               registers[ 8] <= 0;
+               registers[ 9] <= 0;
+               registers[10] <= 0;
+               registers[11] <= 0;

        end
 
        always @(posedge clk)
        end
 
        always @(posedge clk)


@@ -96,6 +126,10 @@ module GBZ80Core(
                                if (rd) rdata <= busdata;
                        buswr <= 0;
                        busrd <= 0;
                                if (rd) rdata <= busdata;
                        buswr <= 0;
                        busrd <= 0;

+                       wr <= 0;
+                       rd <= 0;
+                       address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
+                       wdata <= 8'bxxxxxxxx;

                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin


@@ -113,7 +147,7 @@ module GBZ80Core(
                                                `EXEC_NEXTADDR_PCINC;
                                                rd <= 1;
                                        end
                                                `EXEC_NEXTADDR_PCINC;
                                                rd <= 1;
                                        end

-                               1: begin
+                               1:      begin

                                                `EXEC_INC_PC;
                                                if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};
                                                `EXEC_INC_PC;
                                                if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};


@@ -124,73 +158,545 @@ module GBZ80Core(
                                                        `EXEC_NEWCYCLE;
                                                end
                                        end
                                                        `EXEC_NEWCYCLE;
                                                end
                                        end

-                               2: begin
+                               2:      begin

                                                `EXEC_NEWCYCLE;
                                        end
                                endcase
                        end
                        `INSN_HALT: begin
                                                `EXEC_NEWCYCLE;
                                        end
                                endcase
                        end
                        `INSN_HALT: begin

-                               /* XXX UNIMP */
+                               `EXEC_NEWCYCLE;
+                               /* XXX Interrupts needed for HALT. */

                        end
                        `INSN_LD_HL_reg: begin
                        end
                        `INSN_LD_HL_reg: begin

-                               /* XXX UNIMP */
+                               case (cycle)
+                               0:      begin
+                                               case (opcode[2:0])
+                                               `INSN_reg_A:    wdata <= registers[`REG_A];
+                                               `INSN_reg_B:    wdata <= registers[`REG_B];
+                                               `INSN_reg_C:    wdata <= registers[`REG_C];
+                                               `INSN_reg_D:    wdata <= registers[`REG_D];
+                                               `INSN_reg_E:    wdata <= registers[`REG_E];
+                                               `INSN_reg_H:    wdata <= registers[`REG_H];
+                                               `INSN_reg_L:    wdata <= registers[`REG_L];
+                                               endcase
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               wr <= 1; rd <= 0;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase

                        end
                        `INSN_LD_reg_HL: begin
                        end
                        `INSN_LD_reg_HL: begin

-                               /* XXX UNIMP */
+                               case(cycle)
+                               0:      begin
+                                               address <= {registers[`REG_H], registers[`REG_L]};
+                                               rd <= 1;
+                                       end
+                               1:      begin
+                                               tmp <= rdata;
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase

                        end
                        `INSN_LD_reg_reg: begin
                                `EXEC_INC_PC;
                                `EXEC_NEWCYCLE;
                                case (opcode[2:0])
                        end
                        `INSN_LD_reg_reg: begin
                                `EXEC_INC_PC;
                                `EXEC_NEWCYCLE;
                                case (opcode[2:0])

-                               `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
-                               `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
-                               `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
-                               `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
-                               `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
-                               `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
-                               `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                               `INSN_reg_A:    tmp <= registers[`REG_A];
+                               `INSN_reg_B:    tmp <= registers[`REG_B];
+                               `INSN_reg_C:    tmp <= registers[`REG_C];
+                               `INSN_reg_D:    tmp <= registers[`REG_D];
+                               `INSN_reg_E:    tmp <= registers[`REG_E];
+                               `INSN_reg_H:    tmp <= registers[`REG_H];
+                               `INSN_reg_L:    tmp <= registers[`REG_L];
+                               endcase
+                       end
+                       `INSN_LD_reg_imm16: begin
+                               `EXEC_INC_PC;
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1:      begin
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               2: begin `EXEC_NEWCYCLE; end
+                               endcase
+                       end
+                       `INSN_LD_SP_HL: begin
+                               case (cycle)
+                               0:      begin
+                                               tmp <= registers[`REG_H];
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                               tmp <= registers[`REG_L];
+                                       end
+                               endcase
+                       end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0:      begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_A];
+                                               `INSN_stack_BC: wdata <= registers[`REG_B];
+                                               `INSN_stack_DE: wdata <= registers[`REG_D];
+                                               `INSN_stack_HL: wdata <= registers[`REG_H];
+                                               endcase
+                                       end
+                               1:      begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: wdata <= registers[`REG_F];
+                                               `INSN_stack_BC: wdata <= registers[`REG_C];
+                                               `INSN_stack_DE: wdata <= registers[`REG_E];
+                                               `INSN_stack_HL: wdata <= registers[`REG_L];
+                                               endcase
+                                       end
+                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               2:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDH_AC: begin
+                               case (cycle)
+                               0:      begin
+                                               address <= {8'hFF,registers[`REG_C]};
+                                               if (opcode[4]) begin    // LD A,(C)
+                                                       rd <= 1;
+                                               end else begin
+                                                       wr <= 1;
+                                                       wdata <= registers[`REG_A];
+                                               end
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end

                                endcase
                        end
                                endcase
                        end

+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0:      begin
+                                               address <= {registers[`REG_H],registers[`REG_L]};
+                                               if (opcode[3]) begin    // LDx A, (HL)
+                                                       rd <= 1;
+                                               end else begin
+                                                       wr <= 1;
+                                                       wdata <= registers[`REG_A];
+                                               end
+                                       end
+                               1:      begin
+                                               `EXEC_NEWCYCLE;
+                                               `EXEC_INC_PC;
+                                       end
+                               endcase
+                       end
+                       `INSN_ALU8: begin
+                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+                                       // fffffffff fuck your shit, read from (HL) :(
+                                       rd <= 1;
+                                       address <= {registers[`REG_H], registers[`REG_L]};
+                               end else begin
+                                       `EXEC_NEWCYCLE;
+                                       `EXEC_INC_PC;
+                                       case (opcode[2:0])
+                                       `INSN_reg_A:    tmp <= registers[`REG_A];
+                                       `INSN_reg_B:    tmp <= registers[`REG_B];
+                                       `INSN_reg_C:    tmp <= registers[`REG_C];
+                                       `INSN_reg_D:    tmp <= registers[`REG_D];
+                                       `INSN_reg_E:    tmp <= registers[`REG_E];
+                                       `INSN_reg_H:    tmp <= registers[`REG_H];
+                                       `INSN_reg_L:    tmp <= registers[`REG_L];
+                                       `INSN_reg_dHL:  tmp <= rdata;
+                                       endcase
+                               end
+                       end
+                       `INSN_NOP: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;
+                       end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;           // This goes FIRST in RST
+                                       end
+                               1:      begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               wdata <= registers[`REG_PCH];
+                                       end
+                               2:      begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                               wdata <= registers[`REG_PCL];
+                                       end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                                       {10'b0,opcode[5:3],3'b0};
+                                       end
+                               endcase
+                       end
+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               2:      begin /* twiddle thumbs */ end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                               // do NOT increment PC!
+                                       end
+                               endcase
+                       end
+                       `INSN_CALL: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               2:      begin
+                                               `EXEC_INC_PC;
+                                       end
+                               3:      begin
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               wdata <= registers[`REG_PCH];
+                                               wr <= 1;
+                                       end
+                               4:      begin
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                                               wdata <= registers[`REG_PCL];
+                                               wr <= 1;
+                                       end
+                               5:      begin
+                                               `EXEC_NEWCYCLE; /* do NOT increment the PC */
+                                       end
+                               endcase
+                       end
+                       default:
+                               $stop;

                        endcase
                        state <= `STATE_WRITEBACK;
                end
                `STATE_WRITEBACK: begin
                        casex (opcode)
                        endcase
                        state <= `STATE_WRITEBACK;
                end
                `STATE_WRITEBACK: begin
                        casex (opcode)

-                               `INSN_LD_reg_imm8:
-                                       case (cycle)
-                                       0: cycle <= 1;
-                                       1: case (opcode[5:3])
-                                               `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
-                                               `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
-                                               `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
-                                               `INSN_reg_D:    begin registers[`REG_D] <= rdata; cycle <= 0; end
-                                               `INSN_reg_E:    begin registers[`REG_E] <= rdata; cycle <= 0; end
-                                               `INSN_reg_H:    begin registers[`REG_H] <= rdata; cycle <= 0; end
-                                               `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
-                                               `INSN_reg_dHL:  cycle <= 2;
-                                               endcase
-                                       2: cycle <= 0;
+                       `INSN_LD_reg_imm8:
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      case (opcode[5:3])
+                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
+                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
+                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
+                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; cycle <= 0; end
+                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; cycle <= 0; end
+                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; cycle <= 0; end
+                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
+                                       `INSN_reg_dHL:  cycle <= 2;

                                        endcase
                                        endcase

-                               `INSN_HALT: begin
-                                       /* XXX UNIMP */
-                               end
-                               `INSN_LD_HL_reg: begin
-                                       /* XXX UNIMP */
-                               end
-                               `INSN_LD_reg_HL: begin
-                                       /* XXX UNIMP */
-                               end
-                               `INSN_LD_reg_reg: begin
+                               2:      cycle <= 0;
+                               endcase
+                       `INSN_HALT: begin
+                               /* Nothing needs happen here. */
+                               /* XXX Interrupts needed for HALT. */
+                       end
+                       `INSN_LD_HL_reg: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      cycle <= 0;
+                               endcase
+                       end
+                       `INSN_LD_reg_HL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               case (opcode[5:3])
+                                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                                               `INSN_reg_L:    registers[`REG_L] <= tmp;
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_reg_reg: begin
+                               case (opcode[5:3])
+                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                               `INSN_reg_L:    registers[`REG_L] <= tmp;
+                               endcase
+                       end
+                       `INSN_LD_reg_imm16: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
+                                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
+                                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
+                                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
+                                               endcase
+                                               cycle <= 2;
+                                       end
+                               2: begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
+                                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
+                                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
+                                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LD_SP_HL: begin
+                               case (cycle)
+                               0: begin
+                                               cycle <= 1;
+                                               registers[`REG_SPH] <= tmp;
+                                       end
+                               1: begin
+                                               cycle <= 0;
+                                               registers[`REG_SPL] <= tmp;
+                                       end
+                               endcase
+                       end
+                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
+                               case (cycle)
+                               0: begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 1;
+                                       end
+                               1:      begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               cycle <= 2;
+                                       end
+                               2:      cycle <= 3;
+                               3:      cycle <= 0;
+                               endcase
+                       end
+                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                               case (cycle)
+                               0:      begin
+                                               cycle <= 1;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               1:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_F] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_C] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_E] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_L] <= rdata;
+                                               endcase
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                               cycle <= 2;
+                                       end
+                               2:      begin
+                                               case (opcode[5:4])
+                                               `INSN_stack_AF: registers[`REG_A] <= rdata;
+                                               `INSN_stack_BC: registers[`REG_B] <= rdata;
+                                               `INSN_stack_DE: registers[`REG_D] <= rdata;
+                                               `INSN_stack_HL: registers[`REG_H] <= rdata;
+                                               endcase
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDH_AC: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1: begin
+                                               cycle <= 0;
+                                               if (opcode[4])
+                                                       registers[`REG_A] <= rdata;
+                                       end
+                               endcase
+                       end
+                       `INSN_LDx_AHL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 0;
+                                               if (opcode[3])
+                                                       registers[`REG_A] <= rdata;
+                                               {registers[`REG_H],registers[`REG_L]} <=
+                                                       opcode[4] ? // if set, LDD, else LDI
+                                                       ({registers[`REG_H],registers[`REG_L]} - 1) :
+                                                       ({registers[`REG_H],registers[`REG_L]} + 1);
+                                       end
+                               endcase
+                       end
+                       `INSN_ALU8: begin
+                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
+                                       /* Sit on our asses. */
+                                       cycle <= 1;
+                               end else begin          /* Actually do the computation! */

                                        case (opcode[5:3])
                                        case (opcode[5:3])

-                                       `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
-                                       `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
-                                       `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
-                                       `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
-                                       `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
-                                       `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
-                                       `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                       `INSN_alu_ADD: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] + tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b0,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_ADC: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b0,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_AND: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] & tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+                                                         3'b010,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_OR: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] | tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+                                                         3'b000,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_XOR: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] ^ tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+                                                         3'b000,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       default:
+                                               $stop;

                                        endcase
                                end
                                        endcase
                                end

+                       end
+                       `INSN_NOP: begin /* NOP! */ end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      cycle <= 2;
+                               2:      cycle <= 3;
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                       end
+                               endcase
+                       end
+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 2;
+                                               registers[`REG_PCL] <= rdata;
+                                       end
+                               2:      begin
+                                               cycle <= 3;
+                                               registers[`REG_PCH] <= rdata;
+                                       end
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+                                               if (opcode[4])  /* RETI */
+                                                       ie <= 1;
+                                       end
+                               endcase
+                       end
+                       `INSN_CALL: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 2;
+                                               tmp <= rdata;   // tmp contains newpcl
+                                       end
+                               2:      begin
+                                               cycle <= 3;
+                                               tmp2 <= rdata;  // tmp2 contains newpch
+                                       end
+                               3: begin
+                                               cycle <= 4;
+                                       end
+                               4: begin
+                                               cycle <= 5;
+                                               registers[`REG_PCH] <= tmp2;
+                                       end
+                               5: begin
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                                               registers[`REG_PCL] <= tmp;
+                                               cycle <= 0;
+                                       end
+                               endcase
+                       end
+                       default:
+                               $stop;

                        endcase
                        state <= `STATE_FETCH;
                end
                        endcase
                        state <= `STATE_FETCH;
                end


@@ -198,14 +704,57 @@ module GBZ80Core(
 endmodule
 
 `timescale 1ns / 1ps
 endmodule
 
 `timescale 1ns / 1ps

+module ROM(
+       input [15:0] address,
+       inout [7:0] data,
+       input wr, rd);
+
+       reg [7:0] rom [2047:0];
+       initial $readmemh("rom.hex", rom);
+
+       wire decode = address[15:13] == 0;
+       reg [7:0] odata;
+       wire idata = data;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+       always @(posedge rd)
+               if (decode)
+                       odata <= rom[address];
+endmodule
+
+module InternalRAM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+       
+       reg [7:0] ram [8191:0];
+       
+       wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+       reg [7:0] odata;
+       wire idata = data;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+       reg [13:0] diq;
+       initial
+               for (diq = 0; diq < 8191; diq = diq + 1)
+                       ram[diq] = 8'h43;
+       
+       always @(negedge clk)
+       begin
+               if (decode && rd)
+                       odata <= ram[address[12:0]];
+               if (decode && wr)
+                       ram[address[12:0]] <= data;
+       end
+endmodule
+

 module TestBench();
        reg clk = 0;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
 module TestBench();
        reg clk = 0;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;

-       reg [7:0] rom [2047:0];

        
        

-       initial $readmemh("rom.hex", rom);

        always #10 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
        always #10 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),


@@ -213,5 +762,17 @@ module TestBench();
                .busdata(data),
                .buswr(wr),
                .busrd(rd));
                .busdata(data),
                .buswr(wr),
                .busrd(rd));

-       assign data = rd ? rom[addr] : 8'bzzzzzzzz;
+       
+       ROM rom(
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd));
+       
+       InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));

 endmodule
 endmodule